AMD's PR system is now totally useless!

[PH0ENIX]

Thankyou, HardWareXpert.

For putting a couple of words that actually made sense in the middle of your completely innaccurate, confusing, and apparently self-invented, posts.

The words i'm referring to of course, could only be 'And' & 'The'.

Never before have I heard the topic of IPC explained in TOTALLY the opposite way of how it works...

"RISC only has to do 2 (or is it 1?) instructions per clock cycle rather than the Athlon 6 per clock and the P4's 9 per clock. The need for RISC's to have higher clock speeds is not a issue at all since they are more effecient (like Athlon is over P4) "

So;
The athlon now has a LOWER IPC than the P4.
The P4 apparently executes 4.5 instructions on both the rising and falling sides of the cycle. Dang - half an instruction... no wonder it's so efficient...
Lack of Clock speed is compensated by... lack of IPC... hmmmm...
And RISC is so good, because it has a poor clock frequency, and few instructions per clock.

Tell me, my friend, did you ever work for Cyrix?

 

[FishTankX]

RISC takes the shotgun aproach. It makes all instructions the same lentgh, shortens or eleminates the encoding, has boatloads of execution units and registers and tries to get decent core frequency and *awesome* IPC combined to beat any X86 processor silly!!

X86 has a fundamental limit of 3 instructions per clock. It's a limit. It's a ceiling. Get over it.

The Athlon achieves close to that, I believe. With either it's FPU or it's ALU.
The P4 tries to get around the limit by having insane clock speed and taking it easy on how many instructions it has to finish in one cycle.
A Power4 just tries to have as many execution units, registers, cache bandwidth, memory bandwidth etc... as possible and pushes up the frequency as far as it will go, thus a shotgun like aproach. Do as many instructions as possible per clock and push up the frequency.

Am I right, Ph0enix?

 

[esc]

some of you ppl are screwed. you say that AMD has only 2% of market share and you expect them to make big a$$$$, money-intensive ads like intel does with those aliens? no way. they best be putting all that money in r&d so that they could top intel even more. i really don't see anything wrong with the creation of the PR rating because i think it was made to save AMD a whole lot of money.

 

[HardWareXpert]

Originally posted by: PH0ENIX
Thankyou, HardWareXpert.

For putting a couple of words that actually made sense in the middle of your completely innaccurate, confusing, and apparently self-invented, posts.

The words i'm referring to of course, could only be 'And' & 'The'.

Never before have I heard the topic of IPC explained in TOTALLY the opposite way of how it works...

"RISC only has to do 2 (or is it 1?) instructions per clock cycle rather than the Athlon 6 per clock and the P4's 9 per clock. The need for RISC's to have higher clock speeds is not a issue at all since they are more effecient (like Athlon is over P4) "

So;
The athlon now has a LOWER IPC than the P4.
The P4 apparently executes 4.5 instructions on both the rising and falling sides of the cycle. Dang - half an instruction... no wonder it's so efficient...
Lack of Clock speed is compensated by... lack of IPC... hmmmm...
And RISC is so good, because it has a poor clock frequency, and few instructions per clock.

Tell me, my friend, did you ever work for Cyrix?

RISC=Reduced Instruction Set Computers

"The instruction set is the hardware "language" in which the software tells the processor what to do. Surprisingly, reducing the size of the instruction set -- eliminating certain instructions based upon a careful quantitative analysis, and requiring these seldom-used instructions to be emulated in software -- can lead to higher performance, for several reasons:

The vacated area of the chip can be used in ways that accelerate the performance of more commonly used instructions, more than compensating for the inevitably degraded performance of the seldom-used instructions.
It becomes easier to optimize the design.
It allows microprocessors to use techniques hitherto restricted to the largest computers.
It simplifies translation from the high-level language in which people program into the instruction set that the hardware understands, resulting in a more efficient program. "

RISC is alot more efficient, lower clocked and able to multi process like no other CPU, all your CGI, NASA, runs RISC.

Our AMD and Intel architectures and massive MHz are inefficient compared to a RISC, Intel do a RISC CPU, AMD is based on RISC.

 

[HardWareXpert]

How do you convince a industry where it's lead to believe that higher MHz means more performance to a lower clocked CPU?, use a PR system in which the lower clocked CPU is able and shown to outperform a higher clocked CPU.

1. AMD's white paper on PR system have Mhz of equivalent 1600+, 1700+, 1800+ showing.

2. People that are bothered about the MHz, ask the vendor your buying it from.

3. Most vendors of AMD CPU's have the equivalent Mhz showing anyway.

4. Research the product as most if not all have a website, info and specifications about it.


Damn edits, doing two jobs at once.

 

[RedShirt]

What's to stop Intel from calling their 3 gigahertz processor, the Pentium IV 10000?

Maybe this processor is equivalent to a 386 running at 10000 MHz?

People are trying to justify the rating system saying its close to a Pentium IV now, but the system will continously change.

Take code writing for example, good codewriters don't just write different versions of code and then test each version for speed, they know things are going to change in the future. For instance, maybe some new processor will come out that halves the cycles needed for the multiply or divide instructions. This is why code writers use something called BIG O. If something is BIG 0 n^2 it takes n^2 steps to do the computation. BIG 0 n takes just n steps and is better. The programmer will probably opt to use the Big O n process, even if it takes more time to run on current machines (unless the time is substantually more).

Programmers know technology changes and writing code to work well on only todays machines is not a good idea since something that takes less steps, but uses more cycles (in todays processors) may, and probably will use less cycles in later processors.

So, I guess I'm trying to compare what AMD is doing with this. They are comparing their processor with the Pentium IV (they may not admit thats what they are doing, but it is), and their rating system is flawed because when Intel changes things, the Pentium IV gets better, and the scale just doesn't work.

 

[AGodspeed]

What's to stop Intel from calling their 3 gigahertz processor, the Pentium IV 10000?

Maybe this processor is equivalent to a 386 running at 10000 MHz?

And then you say:

They [AMD] are comparing their processor with the Pentium IV (they may not admit thats what they are doing, but it is)

If you agree that AMD's PR rating is measured up against Pentium 4 processors (not IV btw ) then there's obviously no validaty to your 386 statement.

You've still left quite a few questions unanswered, like:

1. Why changing the PR rating to better relate to the Pentium 4's performance is a bad thing as you claim.
2. Whether the consumer would be better served buying a 1.7GHz P4 system instead of a 1.67GHz Athlon XP system for the same price as would occur if there were no PR rating.
3. Whether it's sensible to suggest that an unbiased 3rd party vendor should dictate AMD's marketing (in regards to the PR rating that is) when it's quite clear that the PR rating is already a good (and conservative) measure of total application performance.

 

[RedShirt]

Originally posted by: AGodspeed
What's to stop Intel from calling their 3 gigahertz processor, the Pentium IV 10000?

Maybe this processor is equivalent to a 386 running at 10000 MHz?

And then you say:

They [AMD] are comparing their processor with the Pentium IV (they may not admit thats what they are doing, but it is)

If you agree that AMD's PR rating is measured up against Pentium 4 processors (not IV btw ) then there's obviously no validaty to your 386 statement.

You've still left quite a few questions unanswered, like:

1. Why changing the PR rating to better relate to the Pentium 4's performance is a bad thing as you claim.
2. Whether the consumer would be better served buying a 1.7GHz P4 system instead of a 1.67GHz Athlon XP system for the same price as would occur if there were no PR rating.
3. Whether it's sensible to suggest that an unbiased 3rd party vendor should dictate AMD's marketing (in regards to the PR rating that is) when it's quite clear that the PR rating is already a good (and conservative) measure of total application performance.

I have answered all of these questions, please read my previous posts.

 

[Priit]

RISC is alot more efficient, lower clocked and able to multi process like no other CPU, all your CGI, NASA, runs RISC.

Our AMD and Intel architectures and massive MHz are inefficient compared to a RISC, Intel do a RISC CPU, AMD is based on RISC.

Yes, Itanium is a RISC processor (more-less), but P4 is not. So what exactly do you mean by the last sentence? Both P4 and Athlon are RISC processors from inside, all x86 processors starting from PPro/K6 are (complex x86 instructions are converted into smaller, RISC-like instructions and executed in parallel). IMO biggest performance boost in RISC processors comes from fixed length instructions (all instructions take about same time to execute) compared to CISC (x86) variable lenght instructions: this allows to do things in parallel much more easily. BTW, RISC-x86 is registered trademark of AMD (or was that x86-RISC)

 

[HardWareXpert]

I'm just saying Intel do a full RISC CPU.