Thankyou, HardWareXpert.
For putting a couple of words that actually made sense in the middle of your completely innaccurate, confusing, and apparently self-invented, posts.
The words i'm referring to of course, could only be 'And' & 'The'.
Never before have I heard the topic of IPC explained in TOTALLY the opposite way of how it works...
"RISC only has to do 2 (or is it 1?) instructions per clock cycle rather than the Athlon 6 per clock and the P4's 9 per clock. The need for RISC's to have higher clock speeds is not a issue at all since they are more effecient (like Athlon is over P4) "
So;
The athlon now has a LOWER IPC than the P4.
The P4 apparently executes 4.5 instructions on both the rising and falling sides of the cycle. Dang - half an instruction... no wonder it's so efficient...
Lack of Clock speed is compensated by... lack of IPC... hmmmm...
And RISC is so good, because it has a poor clock frequency, and few instructions per clock.
Tell me, my friend, did you ever work for Cyrix?
For putting a couple of words that actually made sense in the middle of your completely innaccurate, confusing, and apparently self-invented, posts.
The words i'm referring to of course, could only be 'And' & 'The'.
Never before have I heard the topic of IPC explained in TOTALLY the opposite way of how it works...
"RISC only has to do 2 (or is it 1?) instructions per clock cycle rather than the Athlon 6 per clock and the P4's 9 per clock. The need for RISC's to have higher clock speeds is not a issue at all since they are more effecient (like Athlon is over P4) "
So;
The athlon now has a LOWER IPC than the P4.
The P4 apparently executes 4.5 instructions on both the rising and falling sides of the cycle. Dang - half an instruction... no wonder it's so efficient...
Lack of Clock speed is compensated by... lack of IPC... hmmmm...
And RISC is so good, because it has a poor clock frequency, and few instructions per clock.
Tell me, my friend, did you ever work for Cyrix?