http://www.kitguru.net/components/g...third-iteration-of-gcn-architecture-revealed/One of the key features of the third-generation GCN is updated instruction set architecture (ISA). While there are not a lot of details available at the moment, expect the Tonga and other GPUs based on the GCN 1.2 to support certain new capabilities that improve its overall efficiency when it comes to computing.
Another thing featured by the new GCN is yet again improved tessellation/geometry processing performance. It is unclear whether AMD redesigned its geometry processors in general, or just increased their amount, but tessellation should work better on the GCN 1.2 compared to previous-gen GPUs.
To reduce requirements for memory bandwidth and improve performance in high resolutions, the GCN 1.2 supports delta colour compression. The latter is an image compression technique that encodes a row of pixels by replacing their colour information with values that represent difference between subsequent pixels (e.g. if one pixel in RGB format is 255:0:0, the other one is 255:1:1, the third one is 255:2:0, then with delta compression the sequence can be represented as 255:0:0, 0:1:1, 0:1:-1).
The GCN 1.2-based GPUs will also feature a new multimedia engine which comprises of universal video decoder 6.0 (UVD 6) and video encoder engine 3.1 (VCE 3.1) technologies as well as a new high-quality scaler for video. There is no word about support for ultra-high-definition (UVD) video codecs, such as H.265/HEVC or VP9, so it looks like the new GPUs will not support them.
To reduce requirements for memory bandwidth and improve performance in high resolutions, the GCN 1.2 supports delta colour compression. The latter is an image compression technique that encodes a row of pixels by replacing their colour information with values that represent difference between subsequent pixels (e.g. if one pixel in RGB format is 255:0:0, the other one is 255:1:1, the third one is 255:2:0, then with delta compression the sequence can be represented as 255:0:0, 0:1:1, 0:1:-1).
KitGuru Says: The GCN 1.2 looks very promising on paper. It will be interesting to learn about all of its innovations in-depth…
I wonder if this card has done a Maxwell, and put a bigger cache on die? That could help make up for the narrower memory interface.
Somewhere (AMD slides probably) was disclosed that indeed the CUs sport beefer chaches. Both caches and the pixel color value delta compression technique would incur into better VRAM bandwith efficiency.´
It was due time. Sadly i'm on the same boat that thinks this card should be the original 280x/280. Lets see what approach pays off: a big architectural change between 2 generation of cards, with a little tweak in between like NVs Gx1xx then Gx2xx scheme, or AMD's incremental and evolutive changes to given architectural until there is a new far bigger and radical change from uarch (like VLIW to GCN was compared to NV's Fermi to Kepler to Maxwell).
Actually should have been the HD 7950 and 7970 since the GTX 680/670 supported it. On the flip side those cards had a wider bus with more VRAM so they went the route of sacrificing efficency and added costs instead.
As someone stated before in this thread, these will definitely be a lower cost to manufacture, which is what Nvidia has been doing for 2 years + now.
I dont recommend 4gb in xfire setup unless you have too much money to throw away
The problem with that statement is that AMD explicitly denied it. The initial allegation was that Tahiti has 8 pure redundant CUs (for a total of 40, with only 32 active.) That's an incredible amount of redundancy that can't possibly be exploited profitably over the lifetime of a product. It makes much more sense to sell partially disabled products initially and then deploy fully enabled ones later on, which is exactly what Nvidia did for GK110. GK104 was small enough for it not to really matter. A 1 out of 5 redundancy ratio is a staggering amount of real estate wasted that becomes a bigger liability with time. AMD engineers are not stupid. If you look at typical redundancy ratios, as used in RAMs etc., you get ratios of 1 out of 128 and such. The reason for this is that redundancy math is one of extremely rapid diminishing returns.- Tahiti had added redundancy (which incurred in bigger die area besides the area penalty to sport a 1.5x wider bus and higher DP rate) to sport better yields.
Yes, because correlation always means causation. /sThis allowed not only AMD to have a few months head start compared to NV, but also have a better yield progression curve than NV, because their design was mostly die area optimized at the expense of yields.
Might have, but unlikely. GTX680 had a die that was small enough (300mm2) for it not to matter all that much. And whatever wasn't perfect could be used anyway for GTX670. That's a crucial point you forgot: the vast majority of nonfunctional dies that you tally up as a negative for GTX680 could be reused for GTX670, which arrived on the scene just a couple of months later. So they were never a loss in the first place.- Having better % yields with fewer total dies (functional + nonfuctional ones) per wafer might be roughly the same cost per functional die than having more dies per wafer but lower yield rate.
You have product that takes 3 years to develop. What do you think is more likely? That this extra redundancy made a difference in time-to-market of 2 months or that 2 months in a large engineering project are in the noise?Overal AMD's design decisions behind Tahiti were OK considering it allowed them to have a head start on the 28nm node by shipping products earlier, and reach better yield rates earlier than NV to compensate the bigger die area as a consequence because of the point explained earlier.
Agreed....the rest of your statement...
As far as I understand, redundancy (yield improving design, to be technically more correct) can go down to a level of individual transistors. Especially with the power and clock domains a design that is targeted primarily for higher yields instead of die size can also net huge improvements in time to market, power consumption and clock speed. Consensus is that Nvidia learned this the hard way with GF100.The problem with that statement is that AMD explicitly denied it. The initial allegation was that Tahiti has 8 pure redundant CUs (for a total of 40, with only 32 active.) That's an incredible amount of redundancy that can't possibly be exploited profitably over the lifetime of a product.
We have been far exceeding this level of redundancy for several nodes now afaik, especially if you look at the whole system with layered redundancy. ECC alone has a penalty of 12.5%, and that is just the last level of 'redundancy' (not redundancy per se, but matching goals).If you look at typical redundancy ratios, as used in RAMs etc., you get ratios of 1 out of 128 and such.
The problem with that statement is that AMD explicitly denied it. The initial allegation was that Tahiti has 8 pure redundant CUs (for a total of 40, with only 32 active.)
GK104 and GK108 were both ready at the same time as AMD's 28nm products.
The difference is that nVidia had ~2/3 of the market so they needed much more volume.
That's the reason why their Q1 and Q2 was down in revenue because their were the 28nm supply constraint nearly the full year.
My excuse-o-meter is tingling with this post.
So every time that NV launched on par with AMD on a new node, they actually had their working sillicon earlier? Please dont kid yourself.
Do the reviews come tomorrow (Sept. 2nd)?
I am amazed no one broke NDA.