Analyst: Intel to endorse SOI at 22-nm

[Idontcare]

Analyst: Intel to endorse SOI at 22-nm

''We believe Intel will introduce a germanium (III V) channel and full depleted SOI at 22-nm. This will give Intel a quantum leap in performance over what they are achieving and leave competitors 3-5 years behind. The 22-nm process should be in manufacturing at Intel in Q4:CY11,’’ said Gus Richard, an analyst with Piper Jaffray & Co., in a report.

http://www.eetimes.com/electronics-news/4210354/Analyst--Intel-to-endorse-SOI-at-22-nm-semiconductor

Interesting.

 

[universeis42]

Poor AMD...

 

[cbn]

How would this affect their computer chip cooling?

In the past, Intel has consistently increased clockspeeds despite xtor gate density increasing. (Q6600 GO stepping was capable of 3.5-3.6 GHz on 65nm. Core i7 920 DO stepping was capable of 4.0 Ghz on 45nm.... and now it looks like almost halfway through 32nm Intel is reporting Sandy Bridge quad core at 4.9 Ghz with the tall stock cooler).

Are we talking an even greater clockspeed jump at 22nm? Or are the gains coming from other areas like reduction of manufacturing costs? Maybe a combination of both performance and cost reduction (greater than what would normally be expected at 22nm)?

 

[Daedalus685]

I hate buzz words... Quantum leap, and years ahead of the competition?

They are already appreciably ahead of other such fabs, but I don't quite beleive this will all of a sudden double or some such what I would have already expected 22nm to provide.

At any rate, it is wonderful they believe that SOi and III-V willbe at the same time. We'll see.

On that note though, the quote says "Leave competitors 3-5 years behind." Does that indicate they think the competitions III-V is years behind theirs.. or that the competition is 3 or 5 years behind?

 

[cbn]

On that note though, the quote says "Leave competitors 3-5 years behind." Does that indicate they think the competitions III-V is years behind theirs.. or that the competition is 3 or 5 years behind?

3-5 years ahead of the competition sounds like a massive jump forward. Wouldn't that sort of gap normally be associated with two process nodes apart (eg 16nm vs 32nm) rather than one process node (eg 22nm vs 32nm)apart?

 

[Daedalus685]

3-5 years ahead of the competition sounds like a massive jump forward. Wouldn't that sort of gap normally be associated with two process nodes apart (eg 16nm vs 32nm) rather than one process node (eg 22nm vs 32nm)apart?

Yeah, that is what I thought. They are either buzzingly over stating the lead Intel has/will have (by no means is it small but half a decade is a bit intense) or simply meant that the introduction of a III V channel is going to happen there first.. Since they used Arabic numerals I assume they mean it in hyperbole but it is an odd occurring to use the range 3-5 years right beside talking about the germanium.

 

[IntelUser2000]

There might be a chance but a very little one. Recently Intel claimed(twice already!) that both III-IV and MugFET tech is risky and likely stick to planar for 22nm. Even at 15nm, one or the other is likely, not both.

 

[TuxDave]

Interesting.

I guess....

 

[cbn]

What sort of opinions do people have on Intel's market positioning at 22nm.

According to Wikipedia, "Ivy Bridge" will be "quad core" for the default processor?

Where does that leave the mainstream? (I am referring to the mobile market in particular)

 

[ilkhan]

Basically, "we'll see". :/ Ivy may reach down to dual cores, especially for mobile. It'll probably depend on how low Intel can get the quad core TDPs. They may end up having to cut clocks to get the ULV chips if they don't do dual cores.

 

[Idontcare]

I guess....

Well it (the rumoring) is your own damn fault After what you did with HK/MG the stage is set for folks to anticipate similar "about face" changes in position from Intel when new nodes are released.

Soitec seems to be on a big FD-SOI kick these days:

Timescales

[FONT=Arial,Arial][FONT=Arial,Arial]FD-SOI CMOS technology platform is under development at leading edge technology R&D centers and is on a path to intercept the 22nm/20nm node for mainstream Low Power design. Soitec is already in a position to sample wafers for complete development and qualification of next CMOS node in line with the very tight specifications required to get full benefits of FD-SOI (like top silicon uniformity to be controlled within a few Angstroms), and will be ready to deliver high volumes in 2011. [/FONT]
[/FONT]
http://www.soitec.com/pdf/SOIconsortium_FDSOI_design.pdf

Now I doubt Intel would find itself needing FD-SOI for high-performance apps, but the mobile variant of the 22nm node would probably only stand to benefit from FD-SOI when it comes to the things we want our mobile devices to be really really good at (low to zero standy power usage).

And lastly we have this comment from Soitec regarding FD-SOI TAM and timeline:

Q5- FD-SOI mandates tight wafer specifications : can this be manufactured, who will produce such wafers and when can high volume production start?

A: ...Soitec is already in a position to sample FD-SOI wafers for complete development and qualification of the next CMOS node in line with these tight specifications, and will be ready to deliver high volumes in 2011.

Global capacity for 300mm diameter SOI wafers at Soitec is planned to be of the order of 160 Kwafers/month in 2012. Based on forecasted TAM (Total Available Market) and the anticipated 22/20nm node introduction scenario, this covers estimated market needs until 2014 and can be incrementally increased.

http://www.soitec.com/pdf/SOIconsortium_FDSOI_QA.pdf

There is no way that GloFo+IBM are going to consume 160kwpm capacity...these guys are geared up to support a sizable increase in the global market usage of FD-SOI come 2012 and there is really only one company on the planet right now who is going to have 22nm in production in 2012...

 

[IntelUser2000]

There is no way that GloFo+IBM are going to consume 160kwpm capacity...these guys are geared up to support a sizable increase in the global market usage of FD-SOI come 2012 and there is really only one company on the planet right now who is going to have 22nm in production in 2012...

Yea but Intel will have buyable products by 2012 not just "producing" it which usually means "little after" what they say. Kinda like how Intel claims 2011 22nm production but with products in 2012. A year after 2012 seems right for AMD/IBM, although I agree about wpm numbers being high.

Intel at 32nm has 4 fabs each capable of churning out 45k wafers. The numbers do seem close. But then again, III-IV on TOP of FD-SOI all in one gen?

 

[WhoBeDaPlaya]

Interesting. I'm already using SOI wafers but for photonics devices.

 

[IntelUser2000]

If Intel gets another jump on AMD this 2.5+ year performance gap could well stretch to 3 or more... Maybe 5 is pushing it but it remains to be seen how much Intel will benefit from SOI.

This isn't PD-SOI AMD or IBM uses, its FD-SOI. Intel said no to the former for the past decade, but FD-SOI was always considered.

 

[Triskain]

Can somebody bring me up to speed regarding the difference between PD-SOI and FD-SOI?

 

[Idontcare]

Yea but Intel will have buyable products by 2012 not just "producing" it which usually means "little after" what they say. Kinda like how Intel claims 2011 22nm production but with products in 2012. A year after 2012 seems right for AMD/IBM, although I agree about wpm numbers being high.

Intel at 32nm has 4 fabs each capable of churning out 45k wafers. The numbers do seem close. But then again, III-IV on TOP of FD-SOI all in one gen?

Looking at the gap at 32nm...to whatever extent Intel has 22nm in production in 2012 I don't think we'll see IBM/GloFo/TSMC operating their 22nm at that same extent until 2014.

To be sure that's just an opinion, but it is an opinion that is based on accounting for what lots of little birds are telling me.

My point with the SOI timeline and TAM data above wasn't to say it was proof that Intel is going SOI as the analyst says...it was just my way of saying that some sanity checks on basic reality requirements in the industry do not immediately rule out the possibility.

Now if Soitec (which has some +80% marketshare in SOI) came out and said "we will have 65 kwpm SOI capacity in 2012" then that would be a data point that would cast much doubt over the analyst's rumor because there would be a glaring infrastructure gap.

Much like if someone were to float a rumor that Intel was going to produce 22nm on 450mm wafers...such a rumor could be immediately ruled out as false because there is no way the infrastructure necessary for tooling up a production fab with 450mm wafers will be manufacturing-ready in ~12months.

III-V on SOI is not implausible either. We ram so much dopant into the silicon now that it is a fuzzy definition on when the silicon becomes more of a type III or type V material anyways. Same with SiGe. Not saying it is likely Intel is doing III-V on SOI, just saying at this time there isn't anything overtly contradictory about the rumor, it ranks high on the plausible meter.

 

[Idontcare]

Can somebody bring me up to speed regarding the difference between PD-SOI and FD-SOI?

See the intro section of this pdf whitepaper: http://www.soitec.com/pdf/SOIconsortium_FDSOI_design.pdf

 

[Phynaz]

They did say "quantum leap in performance" which implies CPU performance rather than process nodes.

I would read that as transistor performance, not CPU performance.

Also note, performance does not necessarily mean speed. Performance could mean many things such as power profile, yield, cost etc..

 

[taltamir]

I hate buzz words... Quantum leap, and years ahead of the competition?

its funny, because "a quantum (plural: quanta) is the minimum amount of any physical entity involved in an interaction"...
This makes a quantum leap the smallest possible leap you could make.

 

[Martimus]

See the intro section of this pdf whitepaper: http://www.soitec.com/pdf/SOIconsortium_FDSOI_design.pdf

That is a very interesting paper. Thanks for the link.

 

[ModestGamer]

They did say "quantum leap in performance" which implies CPU performance rather than process nodes. If that is the case it's not as far fetched as some may think.

Intel is already 2+ years ahead of AMD on the performance curve. This may sound extreme to some, but think back to the Nehalem launch 2 years ago, the fastest chip then was the i7 965. Fast forward to today and the venerable i7 965 is still significantly faster than the fastest AMD chip, the X6 1090T. AMD in all likelyhood won't be able to exceed i7 965 levels of performance until Bulldozer hits in H2 2011. That would put them 2.5+ years behind Intel on the performance front.

If Intel gets another jump on AMD this 2.5+ year performance gap could well stretch to 3 or more... Maybe 5 is pushing it but it remains to be seen how much Intel will benefit from SOI.

I wonder what benefit we shall get with transistor size as interconnect latency becomes a overiding factor regardless of node size. IE the limit of the speed of electrons will become a bottle neck regardles of how small they make the transistor.

 

[taltamir]

I wonder what benefit we shall get with transistor size as interconnect latency becomes a overiding factor regardless of node size. IE the limit of the speed of electrons will become a bottle neck regardles of how small they make the transistor.

thats when you use some of those extra transistors to put more components closer... say, by making a single chip with the CPU, memory controller, IO controller, and GPU... the only thing not already merged is the GPU, and that will be merged starting with fusion and sandy bridge.
Also they will be switching to optical interconnects so its the speed of photons... not that it matters, an electric propagates at the speed of light anyways... although an interconnect is limited to about 0.6c because of its construction.

 

[ModestGamer]

thats when you use some of those extra transistors to put more components closer... say, by making a single chip with the CPU, memory controller, IO controller, and GPU... the only thing not already merged is the GPU, and that will be merged starting with fusion and sandy bridge.
Also they will be switching to optical interconnects so its the speed of photons... not that it matters, an electric propagates at the speed of light anyways... although an interconnect is limited to about 0.6c because of its construction.

Hence my point. 22nm is right about at the limits of gains for node size. AMD and everyone else knows this. the only tangiable benefit will be transistor density and power consumption.

I don't see optical interconnects being viable at this scale for a long time to come.

 

[taltamir]

Hence my point. 22nm is right about at the limits of gains for node size.
AMD and everyone else knows this. the only tangiable benefit will be transistor density and power consumption.

Not at all... 22nm is when merging them makes a noticeable difference, decreasing size still provides a GREATER benefit then merging, but merging is now finally useful. We still have severe temperature and transistor limitations on merged products such that the high end is going to remain unmerged... clearly there is much room for improvement in transistor density and size.

I don't see optical interconnects being viable at this scale for a long time to come.

light-peak will be available starting Q1 2011. but there is simply no justification in using it yet. The whole notion of performing calculations with "pure light" is moronic "art major physics" from FuFa (futuristic fantasy) stories. (i am not dignifying them with the name science fiction)
Anyways, as I was saying, using light based interconnects will do NOTHING to increase latency. it will only decrease power consumption, and increase range (by eliminating interference issues) and increase bandwidth (multiplexing).

 

[ModestGamer]

Not at all... 22nm is when merging them makes a noticeable difference, decreasing size still provides a GREATER benefit then merging, but merging is now finally useful. We still have severe temperature and transistor limitations on merged products such that the high end is going to remain unmerged... clearly there is much room for improvement in transistor density and size.

If your talking about integration of more features into the silcone die space. this will definately increase performance. But then everything will start looking like a MCU. hmmmm I think I siad this a few months ago. At some point soon I expect ram, gpu and most if not all outboard chips combined into one large die and stuck to a board. that will leave only perpheral interconect like outboard acessories etc to connect or maybe more copresseing sollutions like GPU.


Either way we will see more integration as currently the cpu handily out runs the ram in most cases and even the hdd. sooner or later we are going to see some very tight board level or chip level or package level integration of a great deal of components.

Alot of the gpu integration I see long term is all about parrelleization, we are hitting the limits of serial processing. GPU combined with serial cpu type work loads will be the way forward but in a few short generations regardless of node sizing, its going to hit a wall to.

I suspect we shall start seeing chips that are more likes cubes instead of more traditional 2d constructs. its going to be the only way to increase computing power given the node size restrictions. I know they layer them already to a small extent.

light-peak will be available starting Q1 2011. but there is simply no justification in using it yet. The whole notion of performing calculations with "pure light" is moronic "art major physics" from FuFa (futuristic fantasy) stories. (i am not dignifying them with the name science fiction)
Anyways, as I was saying, using light based interconnects will do NOTHING to increase latency. it will only decrease power consumption, and increase range (by eliminating interference issues) and increase bandwidth (multiplexing).

did you not read what I siad ? even with light interconnects it won't massively change latencys or transmission speeds. The wall of compute power given our current computing methodologys is reaching its limits. Serial processing has hit the wall or is very very close to it. Even clockspeed increases aren't going to help.