Now how is amd going to improve on that performance of the distributed l3?
Its a disadvantage for them and shows the backside of the design.
A way to look at it is simply. They cant. But so what. Where that matters its a lost market.
Imo the best strategy forward is to entrench and build on your strenght. Not try to make the ocean boil.
7nm high perf with just tuned core and uncore and they are in a very good position. It looks balanced as it is and can do. No need to invent a new bd.
They have PLENTY of options in fact:
1) Continue playing into strong L2 performance by increasing it to 1MB per core. Obvious path with time proven gains, reduced misses, less L3 traffic. ( just keep those morons who designed previous AMD caches away please )
2) Increase L3 per CCX to 12 or 16MB to help keep traffic local to CCX.
4) Keep pumping clock to interconnects and keep rising memory clocks / lowering latency.
3) Increase core count per CCX to 6 ( or one can dream - to 8 ).
if amd increase the core count per ccx, it will lead to increasing latency.
How it will increase latency? Intra-Core latency is const, even IF you keep L3 size and interconnect speed the same, you still have less Inter-CCX traffic just by virtue of having more cores in CCX and not needing to communicate to outside. That is of course amplified if OS scheduler / app is CCX aware.
4Ghz barrier is irrelevant for servers, optimal clocks will not rise to 4Ghz+ for what is 32/48C monsters.
because actually the L3 in the ccx is split to 4 module, that is why when the data spill to L3 and crossing certain size the latency will increase substantially.
While technically you are correct about four L3 slices, the graph does not support the notion. Each slice is 2MB, but notice how 4MB accesses are still 15ns and only 6MB-8MB is deteriorating*. So CCX with 6 or 8 cores, would have 6 or 8 slices of L3 and same "characteristics". If L3 size per slice is increased, that would actually result in performance gain. See what happens @ 8->12? Imagine CCX having 6 cores and 12MB of L3 and putting that point away.
That's what i mean with "2) Increase L3 per CCX to 12 or 16MB to help keep traffic local to CCX." -> by increasing L3 of CCX you are in fact boosting the actual LLC that core can use.
* I think deteriorating happens because L3 is eviction and prefers local slice, so once you go beyond certain point you start evicting older cache lines from local slice, instead of using full size of L3 in CCX.
but by increasing L3 cache you will also increasing the L3 latency across the board, and the topology will be not square, so the core will not balance especially if the data was from the evicted l2 core that locate far away from the center of ccx.
Still not quite sure what you mean.
http://www.chip-architect.com/news/Zen_Summit_Ridge_First.jpg
take this, add 2 more cores to CCX, things are still "square", L3 can be 8MB, 9MB or 12MB or whatever AMD desires and can afford. And L3 is still in the center, with ~same characteristics. SURE average latency could increase a bit due to distance.
Or if they boost L3 to 12MB, then there will be a matching increase in latency.
Double the articles, double the clicks!
Intel is in panic mode. They know the writing is on the wall. Their server market share and margins are going down.Thanks for the laughs, Intel. They don't seem to be as confident in their own products anymore to have to go this low.
Still not quite sure what you mean.
http://www.chip-architect.com/news/Zen_Summit_Ridge_First.jpg
take this, add 2 more cores to CCX, things are still "square", L3 can be 8MB, 9MB or 12MB or whatever AMD desires and can afford. And L3 is still in the center, with ~same characteristics. SURE average latency could increase a bit due to distance.
Why so surprised? Sure Intel are back to bribing suppliers to offer Ryzen with only lethargic memory speeds (well below max supported).
That review is BS IMO, its only benchmarked against older Xeon processors, how lame is that !
They'll probably do an epyc article later. Double the articles, double the clicks!
Ha, sounds about right for Toms
1S is pretty much workstations. Servers are more or less 2S. You do have things like Xeon D though; but that's much lower power and footprint than either Epyc or the typical Xeons.
I think AMD will be having a good quarter.
Selling to amazon google facebook with this marketing from the 80ties only hurts brandvalue and backfires even for uninformed b2b segments. If those "you dont get fired for buying ibm" customers even exist today?? I thought they were extinct. They talk to their customers as if they are braindead and is on a b2c market.German ComputerBase released an article on their own. No benchmarks but afaik they are the first to release more slides from Intel that are quite telling.
https://www.computerbase.de/2017-07/intel-xeon-skylake-sp-purley/3/
Looks like Intel spent quite some time to disparage AMD's approach in its Xeon presentation (around 20 slides focus on that), so the spokesperson previously dissing Epyc as "stitching together 4 desktop dies" is apparently company PR policy now.
http://www.barrons.com/articles/amd-reveals-epyc-details-intel-vows-to-top-it-1497997334
Some of the slides:
Thanks for the laughs, Intel. They don't seem to be as confident in their own products anymore to have to go this low.