[Anandtech] Intel's Architecture Day 2018

[PeterScott]

Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86

I know some bits of this were getting some mention in other threads, but it seems like it was big enough to warrant it's own discussion.

Highlights for me were a new architecture (finally) Sunny cove, that looks to have potential (4-5 wide allocation) to deliver Intels first real IPC improvement in MANY years, and also what should be a nice improvement in the the IGP, and a look at Intels multichip solutions(Foveros) and Intel Big-little.

The Q&A was also somewhat interesting, like where they admit being node-locked on their designs really messed them up, and they will be more node agnostic in the future.

Overall, more actual news than we have seen from Intel in some time.

 

[PotatoWithEarsOnSide]

Have AMD really got the capacity to outsell Intel in any market segment?
I highly doubt it.
Intel would be hurt more by reduced margins than they would anything else.
Dead?
Not by a million miles.

 

[EXCellR8]

Have AMD really got the capacity to outsell Intel in any market segment?

AMD sells more AMD stuff than Intel does.

 

[Yotsugi]

Have AMD really got the capacity to outsell Intel in any market segment?

TSMC sure does.

 

[frozentundra123456]

Maybe.

Yikes.
That's a no from me chief.

Never give up do you? Even one of the most ardent AMD supporters in this forum recognizes how absurd your "Intel is doomed in servers" post is, yet you stick by it. You do realize that repeating something over and over does not necessarily make it true.

 

[Yotsugi]

Never give up do you? Even one of the most ardent AMD supporters in this forum recognizes how absurd your "Intel is doomed in servers" post is, yet you stick by it. You do realize that repeating something over and over does not necessarily make it true.

Yikes^2.

 

[Markfw]

Never give up do you? Even one of the most ardent AMD supporters in this forum recognizes how absurd your "Intel is doomed in servers" post is, yet you stick by it. You do realize that repeating something over and over does not necessarily make it true.

They may not be doomed in servers, but even they admit, that AMD is going to take some market share. The question is how much.

 

[Tuna-Fish]

They say that allocation-width has increased from 4 to 5 but the block diagram shows the main execution units(excl. AGUs) still attached to four ports.

Allocation = register rename. It's basically impossible to sustain 4 ALU ops without mixing in loads, so 5-wide rename is really useful for when your compiler did not manage to turn all your loads into x86 read-alu operations.

 

[ozzy702]

TSMC sure does.

Doubtful. There's a ton of demand for 7nm and capacity will be tapped for the conceivable future.

 

[tamz_msc]

Allocation = register rename. It's basically impossible to sustain 4 ALU ops without mixing in loads, so 5-wide rename is really useful for when your compiler did not manage to turn all your loads into x86 read-alu operations.

So what does width stand for in the context of register renaming? I had allocation width confused with instruction decode, hence my original post.

 

[Spartak]

I'm amazed nobody is seeing what is laid right in front of them.

First, they introduce sunny cove specifically as an architecture independent from it's intended product (icelake).
Second, they mention how they have worked to decouple architecture from process.

Do you really think they would announce this if sunny cove isnt the first example of this? why introduce architecture names for ice lake if this decoupling hasn't occured already?
Why announce all this and not ship products for it beyond mobile which everybody _still_ expects on 10nm. Do you think they'd announce this if there isnt a first example a full year from now?

if it isnt clear to you (and jpiniero especially) sunny cove is a defacto announcement of ice lake architecture on 14nm I dont'know what is.

Willing to take bets sunny cove will appear on desktop next year with you jpiniero. Mind you, not talking about the process node it will ship with.

 

[DrMrLordX]

Huh, I thought one of the takeaways from the Intel Arch Day was that Sunny Cove/IceLake had features coupled to process that made it difficult/impossible to backport to 14nm.

Also it seems like changing the way they name stuff was to let them explain that a product like Lakemont would have a SunnyCove core in it, without bringing up a product like IceLake.

 

[DrMrLordX]

They never announced a Comet Lake S 10 core. That is only rumor.

So are you saying, Comet Lake isn't going to happen?

 

[Spartak]

Huh, I thought one of the takeaways from the Intel Arch Day was that Sunny Cove/IceLake had features coupled to process that made it difficult/impossible to backport to 14nm.

Also it seems like changing the way they name stuff was to let them explain that a product like Lakemont would have a SunnyCove core in it, without bringing up a product like IceLake.

No they said they didnt have the tools available needed for this. And now they do. There isnt anything specific to icelake preventing backporting.

From the article:
Another aspect to Intel’s presentations was that future microarchitectures are likely to be uncoupled from any process technologies. In order to build some resiliency into the company’s product line moving forward, both Raja Koduri and Dr. Murthy Renduchintala explained that future microarchitectures will not be process dependent, and the latest products will come to market on the best process technologies available at the time.

future microarchitectures --> sunny cove
best process technology available ---> 14nm

 

[Carfax83]

Here is a interview by Gamers Nexus concerning Sunny Cove with Intel's Chief Core Architect, Ronak Singhal. Not a particularly insightful interview for industry professionals or engineers, but for non techies, it's quite useful

 

[jpiniero]

if it isnt clear to you (and jpiniero especially) sunny cove is a defacto announcement of ice lake architecture on 14nm I dont'know what is.

Willing to take bets sunny cove will appear on desktop next year with you jpiniero. Mind you, not talking about the process node it will ship with.

I wouldn't rule out Comet Lake coming with Sunny Cove cores. I just think it's very unlikely. Willow Cove on a 14 nm 2020 desktop product is more realistic.

 

[Spartak]

I'm actually wondering how you got to understand exactly the opposite of what they said five times throughtout the interview and article. They literally said it wasn't an issue with process or architecture but with the tools: the rest of the world solves this with abstraction

Hence they introduced architecture names to make this change in their design process explicit.

 

[Dayman1225]

I'm amazed nobody is seeing what is laid right in front of them.

First, they introduce sunny cove specifically as an architecture independent from it's intended product (icelake).
Second, they mention how they have worked to decouple architecture from process.

Do you really think they would announce this if sunny cove isnt the first example of this? why introduce architecture names for ice lake if this decoupling hasn't occured already?
Why announce all this and not ship products for it beyond mobile which everybody _still_ expects on 10nm. Do you think they'd announce this if there isnt a first example a full year from now?

if it isnt clear to you (and jpiniero especially) sunny cove is a defacto announcement of ice lake architecture on 14nm I dont'know what is.

Willing to take bets sunny cove will appear on desktop next year with you jpiniero. Mind you, not talking about the process node it will ship with.

Ronak Singhal said in an interview with GamersNexus that first Sunny Cove products would be on 10nm (Lakefield and ICL Y/U?)

 

[jpiniero]

I think the point is that they will be reusing the same core design for different products, like in the case of Icelake and Lakefield.

 

[Tuna-Fish]

So what does width stand for in the context of register renaming? I had allocation width confused with instruction decode, hence my original post.

The amount of registers that can be renamed per cycle. In a PRF machine, every destination register needs to be renamed during the register rename phase. In older Intel architectures, only 4 of those can pass through the rename phase every cycle, so even if there is a loop that would pass decode at >4 cycle (so from op cache) and would issue to units at >4 per cycle (so to all the alus and some agus), the overall thorughput is fixed at most 4 per cycle. Note that not all instructions require a destination register (example: stores, jumps).

As an example, consider a sequence with a load and 4 adds (unrolled a lot to hide the conditional jump back). It only uses 4 alus and one agu, and at 5 instructions it's less than what can be retrieved per cycle from the op cache, but on all existing Intel cpus it cannot execute at a rate of one iteration per cycle, for two reasons: Intel CPUs can only retire up to 4 instructions per cycle, and they can only allocate up to 4 registers per cycle. They have widened retire, and they have widened allocation, so in future cpus it should execute faster.

This was something that Zen actually has a leg up on current Intel CPUs. It's something that helps SMT/HT more than single-threaded code though, because in real code there usually simply are not that much ILP available. I'd expect a very minor IPC gain for single-threaded, but much higher one for when running two threads on the same core.

This advantage isn't free, though. Register rename width is widely known to be heavily limited by pipeline stage length, that is, choosing to have a wider rename means accepting lower potential maximum clock speeds. This doesn't necessarily mean that clock speeds go down from current ones (once the 10nm process works properly, they might get some additional speed from that), but it does mean they chose to design for slightly lower clocks with higher IPC. This is what the trend seems to be today; with both Zen and Apples designs going for wider but slower.

 

[porcupineLTD]

Doubtful. There's a ton of demand for 7nm and capacity will be tapped for the conceivable future.

Except that isn't true and TSMC will have overcapacity for 7nm until H2 2019 (according to digitimes both Apple and Hisilicon cut a lot of orders).

 

[Spartak]

Ronak Singhal said in an interview with GamersNexus that first Sunny Cove products would be on 10nm (Lakefield and ICL Y/U?)

Yes we all know these will launch. But what are yields and what happens to the desktop later that year?. This isnt about ICL Y/U but the higher power mobile and desktop chips that will be released later and in higher volume.

Higher end mobile is probably a toss depending on volume, performance and yields but I'd say 14nm is most likely.

 

[Yotsugi]

Doubtful. There's a ton of demand for 7nm and capacity will be tapped for the conceivable future.

They, like, literally said H1 2019 is barren for TSMC (thanks, Bitmain & $1k smartphones).
Also it's not like TSMC isn't customer-focused and doesn't expand the capacity frequently.

 

[ozzy702]

They, like, literally said H1 2019 is barren for TSMC (thanks, Bitmain & $1k smartphones).
Also it's not like TSMC isn't customer-focused and doesn't expand the capacity frequently.

Looks like I'm behind. This bodes well for 7nm goodness from AMD on the CPU front and NVIDIA on the GPU front. 2019 got a lot more exciting.

 

[Yotsugi]

Looks like I'm behind. This bodes well for 7nm goodness from AMD on the CPU front and NVIDIA on the GPU front. 2019 got a lot more exciting.

nV isn't shipping anything N7 for majority (maybe the entirety) of 2019.
AMD, ye, gotta feed the hyperscale.

 

[Qwertilot]

"Child of Volta" - compute only - is surely very likely for 2019?