Dammit, why there is no IGP bench over the 35w parts? And why the 35w Carrizo not given a dual-channel ram?
By default, in the US market, there are no Carrizo laptops with cTDP limits up to 35W and dual-channel RAM. So the review is showing you what you can expect out-of-the-box.
Though I think it's stupid that the Y700 was removed from some of the tests.
That is why I've been arguing that aMD should build ALL their SoCs with HBM and even stick flash on there too. And if they can, make their display controllers require a minimum 1080p panel in order to function. I dont know how feasiable that is, but they need to do this to recover their brand image and actually get some real design wins.
They can actually set the system up to boot only with dual-channel RAM, force the OEM to allow cTDPs of up to 35W by removing some of the configurability, and some other stuff like that thar. I'm sure they could cripple dGPU functionality on some chips to force OEMs not to use bad dGPUs as well, and then they could h4x the iGPU to do as you say and only function with a minimum panel size.
OK let me say here that all this crap is AMD FAULT and im dead serious this time.
DONT let the OEM destroy you, but that is exactly what the OEMs did to Carrizo. They completely destroyed a very nice product with awfully bad designed Laptops.
Okay, that's a fair statement. But, you have to ask yourself: why is AMD going through this crap? They launched a successor to mobile Kaveri, and the OEMs decided to use it as a successor to Puma/Jaguar instead (rather than using Carrizo-L in that space). 15W cTDP limits were only supposed to be a thing for a few units, not damn near all of them.
Also, what kind of leverage does AMD really have? If they locked down their system sufficiently to get the system you're talking about, would AMD have gotten any design wins? Getting mobile Kaveri into US laptops was nearly impossible for them. It's like the OEMs said, "give us 15W chips or we ignore you again. We don't want 35W chips, and we don't care if we can save wattage elsewhere by removing junk dGPUs from the BoM. We got a warehouse full of the things and we gotta move em out somewhere".
shouldn't we have 1 carrizo thread like we have 1 skylake thread?
Maybe . . . that's up to the mods. Though the Carrizo thread we have elsewhere is a preview thread, for what it's worth.
Shoulda been eight Excavator cores with 8MB of L3 in AM3+. That would have been a better use in my opinion.
Shhh you might bring he-who-can-not-be-named into the thread.
Seriously though, you have to wonder what process they would have had to use to make 4m/8t Excavator + L3. AMD has yet to use L3 on anything beyond Piledriver (though apparently the L3 issues were "fixed" in the lab, they just haven't implemented it anywhere). If AMD had used HDL in the design and used the same bulk 28nm for 4m XV, you'd be looking at clockspeeds in the 2.5-3 GHz department by default. Does that still sound like a good idea?
(in the server room, for 2014/2015, YES. Elsewhere . . . ehhhh).