AnandtechAMD Carrizo ExcavatorReview

[railven]

That all happened well after it served its purpose. Plus, Tengen lost in court.

That's unrelated to the issue. Again, the Seal didn't actual create quality. It was just a way for Nintendo to limit games on their system. Companies gamed it by creating dummy companies. Other companies didn't even bother and still created games. And this was at the height of Nintendo's popularity (again, I argue the companies doing this to game the SoQ program is what made Nintendo successful.)

The success of 80 Plus shows that consumers respond to such labels. 80 Plus is a problematic and overly complex standard. If it can succeed a simpler and more worthwhile standard can succeed for boards.

Now you're arguing a marketing prospect more than a guarantee of product quality. The 80 Plus certification even had companies gaming it which led to a lot of mistrust. If I recall correctly, they even admitted they weren't testing every single PSU but were awarding Bronze Cert based on manufacturers specs.

 

[Abwx]

From your link..
"One 8 GB RAM module is plugged in onto the motherboard. A second module could be added. Due to a single-channel memory controller adding a second RAM module does not bring a performance gain for the graphics card. Only moving to the fast memory might bring a small performance gain."

Of course since Carrizo-L has only a single channel, it s the APU that make the bus width, if they had soldered a Carrizo instead the second dimm would be connected to the APU second channel..

Indeed the Toshiba satellite with this latter APU is running in dual channel...

 

[The Stilt]

Of course since Carrizo-L has only a single channel, it s the APU that make the bus width, if they had soldered a Carrizo instead the second dimm would be connected to the APU second channel..

Indeed the Toshiba satellite with this latter APU is running in dual channel...

Any Carrizo-L system which has two usable memory slots (on Carrizo-L) will not have dual channel when the Carrizo-L is replaced with Carrizo. Or could you explain how the second memory slot suddenly becomes to connected to MB signals instead of MA?

 

[Burpo]

The answer lies in the "transconductance."

 

[Abwx]

Any Carrizo-L system which has two usable memory slots (on Carrizo-L) will not have dual channel when the Carrizo-L is replaced with Carrizo. Or could you explain how the second memory slot suddenly becomes to connected to MB signals instead of MA?

Because Carrizo-L has different pins for two dims, seen from the outside it s a 128bit bus but the "two channels" are connected (inside the APU) to a single 64 bit bus through a 128bit to 64 bit dispatcher.

That s a different implementation than usual designs where all the RAM dimms are parraleled and where the used dimm is selected with the usual CS command, i guess that it was necessary to have high RAM capacity of 32GB, a pure parrallelisation of 4 dimms wouldnt work well for obvious reasons, ask the guys that do the layouts..

 

[The Stilt]

This gives me cancer

How does changing the APU change the physical traces on the motherboard?

So you are either claiming that the second memory slot on Carrizo-L / Stoney Ridge is not connected to anything (yet it works...) or that replacing the APU changes the pins where the traces from the memory slot connect.

Carrizo-L and Stoney Ridge have:

MA_ADD 15:0
MA_BANK 2:0
MA_CAS_L
MA_CHECK 7:0
MA_CKE 1:0
MA_CLK_HI 7:0
MA_CLK_LO 7:0
MA0_CS_L 1:0
MA1_CS_L 1:0
MA_DATA 63:0
MA_DM 8:0
MA_DQS_H 8:0
MA_DQS_L 8:0
MA_EVENT_L
MA0_ODT 0:1
MA1_ODT 0:1
MA_RAS_L
MA_RESET_L
MA_WE_L
MA_VREF_DQ
MA_ZVDDIO_MEM_S

While Carrizo / Bristol Ridge have identical set for MB too.

You probably think that plugging a Trinity FS1b APU to AM1 motherboard would enable dual channel on those motherboards too? :sneaky:

 

[superstition]

Again, the Seal didn't actual create quality.

Yes, it did. It created a standard that had marketing quality, a meaning that consumers took into account. As long as Nintendo did enough to limit low-grade games the seal did create quality.

It was just a way for Nintendo to limit games on their system.

That's vague enough to support what I was saying. And, I already addressed the conflict of interest bit by pointing out that AMD doesn't have one since it doesn't make boards.

Companies gamed it by creating dummy companies. Other companies didn't even bother and still created games. And this was at the height of Nintendo's popularity (again, I argue the companies doing this to game the SoQ program is what made Nintendo successful.)

The seal's importance was primarily with respect to the initial marketing of the NES. How effective it was after the NES was a success is rather immaterial. The seal was a useful lever to gain trust in a distrustful market. Nintendo even had to tell retailers it would buy back unsold stock to get them to put the NES on its shelves in the beginning.

AMD can improve its brand image by having a seal for AM4. And, if you are correct (that the seal accomplishes absolutely nothing) then it's not going to hurt AM4.

Now you're arguing a marketing prospect more than a guarantee of product quality.

It was never not about marketing. The idea is to have both. A properly-designed standard would prevent egregious products from being made. It would also give consumers a clearer reason to pay for better boards.

The 80 Plus certification even had companies gaming it which led to a lot of mistrust. If I recall correctly, they even admitted they weren't testing every single PSU but were awarding Bronze Cert based on manufacturers specs.

80 Plus has been a success and it has led to better-quality PSUs and more consumer focus on buying better-quality PSUs, even though it is an overly complex standard with flawed testing methodology.

AMD's seal can be better than that.

 

[Abwx]

This gives me cancer

How does changing the APU change the physical traces on the motherboard?

So you are either claiming that the second memory slot on Carrizo-L / Stoney Ridge is not connected to anything (yet it works...) or that replacing the APU changes the pins where the traces from the memory slot connect.

Carrizo-L and Stoney Ridge have:

MA_ADD 15:0
MA_BANK 2:0
MA_CAS_L
MA_CHECK 7:0
MA_CKE 1:0
MA_CLK_HI 7:0
MA_CLK_LO 7:0
MA0_CS_L 1:0
MA1_CS_L 1:0
MA_DATA 63:0
MA_DM 8:0
MA_DQS_H 8:0
MA_DQS_L 8:0
MA_EVENT_L
MA0_ODT 0:1
MA1_ODT 0:1
MA_RAS_L
MA_RESET_L
MA_WE_L
MA_VREF_DQ
MA_ZVDDIO_MEM_S

While Carrizo / Bristol Ridge have identical set for MB too.

You probably think that plugging a Trinity FS1b APU to AM1 motherboard would enable dual channel on those motherboards too? :sneaky:

Let me explain it simply since you confuses adresses and pin count...

Carrizo has 128 pins for the dual channel data bus (plus the parity bits), lets call them pin0-127.

If Carrizo L is to be compatible in the same MB then it means that it has 128 pins as well for the RAM, difference is that the 128 pins are going to a dispatcher (inside the APU as said ad nauseam) that select either the pin0-63 or the pin64-127 at clock rate and dispatch the relevant RAM DIMM to an effective 64 bit bus.

Indeed Kabini support 32GB and designing a MB that can support 4 or even 2 dimms within a single channel and in parrallel mode is not an easy task (see the X99 plateform and its 4 slots/channel...), it is much better to use two 64 bit transmitters rather than a single one, the transistor cost is extremely small while this increase the max frequency of the transmissions lines (traces on the PCB that convey the signals).

 

[Bryf50]

I don't see how people in this thread are reading this review and attacking the Carrizo APU itself. Really, I can't help but be somewhat impressed by Carrizo. Especially the gains they achieved at lower power consumption compared to Kaveri. Looking at the NotebookCheck reviews where they added the second DIMM shows what could've been a fairly competitive product.

If it wasn't for the failure and combined fault of AMD and OEMs to actually release good designs I could've seen myself buying one.

 

[The Stilt]

Let me explain it simply since you confuses adresses and pin count...

Carrizo has 128 pins for the dual channel data bus (plus the parity bits), lets call them pin0-127.

If Carrizo L is to be compatible in the same MB then it means that it has 128 pins as well for the RAM, difference is that the 128 pins are going to a dispatcher (inside the APU as said ad nauseam) that select either the pin0-63 or the pin64-127 at clock rate and dispatch the relevant RAM DIMM to an effective 64 bit bus.

Indeed Kabini support 32GB and designing a MB that can support 4 or even 2 dimms within a single channel and in parrallel mode is not an easy task (see the X99 plateform and its 4 slots/channel...), it is much better to use two 64 bit transmitters rather than a single one, the transistor cost is extremely small while this increase the max frequency of the transmissions lines (traces on the PCB that convey the signals).

Even a broken clock is correct twice in a day, you aren´t.

- 16h family supports two DIMMs max (check 16h BKDG).
- Carrizo-L has 144 pins for the memory, Stoney Ridge has 133 and Carrizo / Bristol Ridge has 294.

The reason why it has twice the connections should be clear to everyone.

There is no point in trying to put any sense in your head, since you don´t understand even the basics. But please do everyone a favor and keep your incorrect information in your own head and do not try to force it down everyones throats.

 

[nismotigerwvu]

I don't see how people in this thread are reading this review and attacking the Carrizo APU itself. Really, I can't help but be somewhat impressed by Carrizo. Especially the gains they achieved at lower power consumption compared to Kaveri. Looking at the NotebookCheck reviews where they added the second DIMM shows what could've been a fairly competitive product.

If it wasn't for the failure and combined fault of AMD and OEMs to actually release good designs I could've seen myself buying one.

I know, right. Compared to Kaveri, they cut down the TDP by ~20% and increased performance by about 20% all while lowering the die size on the same freakin' node! I know there had to be some low hanging fruit they were able to take advantage of, but that's still an impressive piece of engineering. Now the outcome versus Intel was as expected, the manufacturing lead is just too great to overcome right now. However, even in bandwidth starved single channel mode, Carrizo's performance was starting to get near that "close enough" point in a few benchmarks. If AMD really can deliver another 40% increase in IPC without the clocks falling off a cliff, Zen really might be the infusion of competition we've been wishing for.

 

[ElFenix]

Maybe . . . that's up to the mods. Though the Carrizo thread we have elsewhere is a preview thread, for what it's worth.

i am a mod :sneaky:

 

[Burpo]

Even a broken clock is correct twice in a day, you aren´t.

There is no point in trying to put any sense in your head, since you don´t understand even the basics. But please do everyone a favor and keep your incorrect information in your own head and do not try to force it down everyones throats.

And everyone said "Amen" ()

I know, right. Compared to Kaveri, they cut down the TDP by ~20% and increased performance by about 20% all while lowering the die size on the same freakin' node! I know there had to be some low hanging fruit they were able to take advantage of, but that's still an impressive piece of engineering. Now the outcome versus Intel was as expected, the manufacturing lead is just too great to overcome right now. However, even in bandwidth starved single channel mode, Carrizo's performance was starting to get near that "close enough" point in a few benchmarks. If AMD really can deliver another 40% increase in IPC without the clocks falling off a cliff, Zen really might be the infusion of competition we've been wishing for.

Well said.. My thoughts also.. Lets hope..

 

[Abwx]

Even a broken clock is correct twice in a day, you aren´t.

- 16h family supports two DIMMs max (check 16h BKDG).
- Carrizo-L has 144 pins for the memory, Stoney Ridge has 133 and Carrizo / Bristol Ridge has 294.

The reason why it has twice the connections should be clear to everyone.

There is no point in trying to put any sense in your head, since you don´t understand even the basics. But please do everyone a favor and keep your incorrect information in your own head and do not try to force it down everyones throats.

It is clear, it s you that are inventing random explanations to sustain an unsustainable point since you dont understand what is exactly an electronic circuitry, the fact is that RAM buses dont use differential signals so there s only 64 wires for 64 bit.

The 294 pins are for four dimms, each dimm use a 64 bit bus, the four buses are then paired with a dispatcher, same as Carrizo-L but with four dimms and two channels....

If only two dimms are used then Carrizo will use two relevant 64 bit paths, as said there s a 64 bit transmitter per dimm, including in Carrizo..

 

[Phynaz]

I can only believe that abwx gets his information from nosta. 64 bit data paths require 80 pins, and that's just for the data.

Of course ddr uses differential signaling all over the place. I can think of half a dozen off the top of my head.

He also seems to forget about all the address, control, command, clock and feedback signals.

10 minutes of Google can get you all the jedic specs.

 

[USER8000]

From your link..
"One 8 GB RAM module is plugged in onto the motherboard. A second module could be added. Due to a single-channel memory controller adding a second RAM module does not bring a performance gain for the graphics card. Only moving to the fast memory might bring a small performance gain."

The first link is for a Carrizo L laptop and that chip only has a single channel memory controller.

 

[USER8000]

Any Carrizo-L system which has two usable memory slots (on Carrizo-L) will not have dual channel when the Carrizo-L is replaced with Carrizo. Or could you explain how the second memory slot suddenly becomes to connected to MB signals instead of MA?

You do realise that with two SODIMM slots both have to be physically connected to the actual CPU??

If that was not the case,only one SODIMM slot could be used at any time.

The traces have to be there to the CPU socket,so that cost is still there.

People are assuming that since the Kaveri and Beema chip successors pin compatible with a SINGLE common platform,it suddenly means the Excavator based chips are suddenly being shoehorned into the Puma/Jaguar equivalent platform,ie,FT3 successor. If that was the case the platform would be called FT4 and not FP4.

Plus,AMD would have designed the common platform with dual channel memory in mind - if not why bother with all that extra area taken up by a dual channel memory controller in the SOC? They even cut half the L2 cache to save on die area.

Also at least in the UK I have seen far more Carrizo laptops than Carrizo L ones. Makes me wonder whether Carrizo L is more expensive to implement than the old FT3 based platform for the Puma/Jaguar successors.

The new platform makes much more sense for the Kaveri successor as the motherboards will be cheaper to make due to Carrizo being an SOC.

However,not so sure for Carrizo L though.



Edit to post

If not the you will only be seeing one SODIMM slot for any of these systems. Far cheaper to implement especially since 8GB SODIMMs are cheap now,and then having to solder another SODIMM slot which makes things more expensive and increases BOM.

So according to you OEMs are trying to skimp on making the motherboards dual channel capable while at the same time spending more money on adding a pointless second SODIMM slot,when these systems will be shipping with single 4GB or 8GB SODIMMs?

So all that extra time on the production line in man hours,the extra cost of the SODIMM holders,solder,validation,etc for no real reason.

Seems a weird way to save money! :thumbsup:

 

[ShintaiDK]

Even a broken clock is correct twice in a day, you aren´t.

There is no point in trying to put any sense in your head, since you don´t understand even the basics. But please do everyone a favor and keep your incorrect information in your own head and do not try to force it down everyones throats.

+1 :thumbsup:

 

[ShintaiDK]

I can only believe that abwx gets his information from nosta. 64 bit data paths require 80 pins, and that's just for the data.

Of course ddr uses differential signaling all over the place. I can think of half a dozen off the top of my head.

He also seems to forget about all the address, control, command, clock and feedback signals.

10 minutes of Google can get you all the jedic specs.

Its the "TRANSCONDUCTANCE" from the great "EE"!

 

[ShintaiDK]

It is clear, it s you that are inventing random explanations to sustain an unsustainable point since you dont understand what is exactly an electronic circuitry, the fact is that RAM buses dont use differential signals so there s only 64 wires for 64 bit.

The 294 pins are for four dimms, each dimm use a 64 bit bus, the four buses are then paired with a dispatcher, same as Carrizo-L but with four dimms and two channels....

If only two dimms are used then Carrizo will use two relevant 64 bit paths, as said there s a 64 bit transmitter per dimm, including in Carrizo..

Isnt it about time you stop you utter nonsense that you try to spread around. Like it wasn't enough that you couldn't understand basic concepts of Intel CPUs, now you show that you dont have the slightest idea how AMD CPUs work as well. And as always you present zero facts and evidence.

If you got an EE degree, I am the holy roman emperor.

 

[deasd]

Isnt it about time you stop you utter nonsense that you try to spread around. Like it wasn't enough that you couldn't understand basic concepts of Intel CPUs, now you show that you dont have the slightest idea how AMD CPUs work as well. And as always you present zero facts and evidence.

If you got an EE degree, I am the holy roman emperor.

Can't endure anymore, sorry sir. I can't see any valuable post from you in this thread, and even in this forum, just keep putting label on others. I wonder why admin don't ban you permanently after almost 18000+ posts by guys like you.D:

 

[USER8000]

Isnt it about time you stop you utter nonsense that you try to spread around. Like it wasn't enough that you couldn't understand basic concepts of Intel CPUs, now you show that you dont have the slightest idea how AMD CPUs work as well. And as always you present zero facts and evidence.

If you got an EE degree, I am the holy roman emperor.

Did you just call out a forum member??

If you don't like him,put him on ignore.

 

[Abwx]

Isnt it about time you stop you utter nonsense that you try to spread around. Like it wasn't enough that you couldn't understand basic concepts of Intel CPUs, now you show that you dont have the slightest idea how AMD CPUs work as well. And as always you present zero facts and evidence.

If you got an EE degree, I am the holy roman emperor.

It is non sense for you because you dont understand electronic circuitries design, what are your own "facts and evidences"..?. Personal attacks because you know that you know nothing..?.

Indeed what i explained is simple enough to be understood, so if one is still refuting it means that he doesnt even have a basic understanding of what is a simple wire...

 

[Abwx]

Since i have seen Phynaz post through another post i will adress his statement..

For one when i say 128 bit i perfectly know that there s a parity bit added per Byte, i say 128 to keep things easy to understand.

Second is that RAM do not use differential signals, otherwise 128 wires (+ parity bits) would be necessary per dimm, indeed i invite him to check the pin out of a RAM module..

http://www.simmtester.com/page/news/images/dimm/ddr3%20dimm%20pinout.jpg

http://www.simmtester.com/page/news/showpubnews.asp?num=170

http://www.samsung.com/semiconductor/global/file/product/ds_ddr3_4gb_b-die_based_rdimm_rev15-0.pdf

Each bit is conveyed relative to the ground as reference, in a differential wiring there s a + signal and a - signal that are both referenced to the ground but the receiver just use the difference between the +- signals, this allow to almost anihilate the parasistic signals (noise) that could be induced in the transmission lines.

Also at least in the UK I have seen far more Carrizo laptops than Carrizo L ones. Makes me wonder whether Carrizo L is more expensive to implement than the old FT3 based platform for the Puma/Jaguar successors.

Fact is that once the MB is manufactured the cost to solder a Carrizo or a Carrizo-L is the same, the only difference between the two laptops is the APU price delta as well as a negligible difference in the APU power supply.

Actualy the difference will be on the screen and other customisable features since 1080p for instance are used only for Carrizo if we except a HP C-L laptop...

 

[Dresdenboy]

I usually try to take it upon myself to get a detailed knowledge of the brand/idea/whatever I'm defending/promoting/passionate about... tends to save me some embarrassment.

+1 that defenders should be doing that. In this case it was a typical result of little time and not so clear statements.

As I have to keep my spare time down (being 40, with children soon), which also means, I have to manage where I put my time, I still prefer to do research about future tech.