Performance is not just the only goal for Apple having a brilliant in-house SoC design team. It's also a carefully planned out move to retain as much control over their end product. It's amazing how hardware nerds focus so much on benchmarks that they don't get the latter.
I remember reading an article minimizing the performance increase of the iPhone 7 since it was only 40% faster than the A9. LOL. The reality is that Apple has intentionally downplayed what a huge a performance leap they made. I suspect to avoid comparisons with their Pro and computer models. I'm excited to see this processor or an X variant in the iPad Pro and I hope a custom one made for the MacBook.
Indeed. But then again, much of the press echoes what mainstream consumers think about this stuff, partially because they don't really understand it fully.The mainstream tech media lauded Apple for stupid cosmetic crap in the early innings of the smartphone boom and called it "innovative." Now that Apple's technical innovation is starting to be quite serious in chips and other tech, these same people say that iPhone 7 is boring/derivative/etc. Can't help but roll my eyes.
It's not a question of trivial or not, it's an issue of energy economy.On the A10 "Fusion": So is the logical explanation is that A10's big cores are consuming too much power when doing trivial stuff?
Apple's aggressive approach to SoC performance suggests that they want to try to make their own processors for all of their products lines at some point. They don't care about competing with Qualcomm or Samsung as much as they want to be able to beat Intel, at which point they're that much closer to vertical integration for their traditional computing platforms.
But whatever node is being used, the A10 processor is incredibly thin, giving credibility to the reports that TSMC’s InFO packaging technique is being used.
The A10 sits below the Samsung K3RG1G10CM 2-GB LPDDR4 memory. This is similar to the low power mobile DRAM as the one we found in the iPhone 6s. Looking at the X-rays we see the four dies are not stacked, but are spread out across the package. This arrangement keeps the overall package height to a minimum. Assembled in a package-on-package assembly with the A10 InFO packaging technique reduces the total height of PoP significantly.
Now I want to see the die size normalized for wafer price . In any case x'tor density with those 3.2B ones is astounding. Probably the only piece of the silicon that is not crapped up with SRAM and dense logic are the 2 HP cores.So, this makes A10 Fusion the largest iPhone SoC Apple has ever created, but it's actually very similar in size to the original A5 in my iPad 2 (which I am still using with iOS 9). However, the A5 was shrunk later by a significant amount with a die shrink. A10 Fusion is quite a bit smaller than most of the X variants for the iPads though. I wonder if there will be an A10X, and if so, how big it will be.
A10x is on TSMC 10nm.A4: 53.3 mm2 Samsung 45 nm
A5: 122.2 mm2 Samsung 45 nm
A5r2: 69.6 mm2 Samsung 32 nm
A5 (1 core): 37.8 mm2 Samsung 32 nm
A5X: 165 mm2 Samsung 45 nm
A6: 96.7 mm2 Samsung 32 nm
A6X: 123 mm2 Samsung 32 nm
A7: 102 mm2 Samsung 28 nm, over 1 billion transistors
A8: 89 mm2 TSMC 20 nm (although some say Samsung also made some), 2 billion transistors
A8X: 128 mm2 TSMC 20 nm, 3 billion transistors
A9: 96 mm2 Samsung 14 nm, over 2 billion transistors
A9: 104.5 mm2 TSMC 16 nm, over 2 billion transistors
A9X: 147 mm2 TSMC 16 nm
A10: ~125 mm2 TSMC 16 nm, 3.3 billion transistors
So, this makes A10 Fusion the largest iPhone SoC Apple has ever created, but it's actually very similar in size to the original A5 in my iPad 2 (which I am still using with iOS 9). However, the A5 was shrunk later by a significant amount with a die shrink. A10 Fusion is quite a bit smaller than most of the X variants for the iPads though. I wonder if there will be an A10X, and if so, how big it will be.
It's the cell transceiver and amps, the XMM basebands aren't just the modem it's the whole RF stack as well, it was always part of any Intel/Infineon solution.Does anyone know what those Intel RF tranceivers are? I didn't know Intel had such things in their portfolio.
I don't even know how a modem exactly works and how it's made (like does it have an architecture like a CPU, what does it do).It's the cell transceiver and amps, the XMM basebands aren't just the modem it's the whole RF stack as well, it was always part of any Intel/Infineon solution.
With InFO, the wafer package can mix such that the GPU can be 16nm, the various cores 10nm, etc. Now we will need to wait for the X-Rays to ascertain which part is at which scaling. Unless Apple tells us outright. Typically SRAM is the first to shrink. Look at the SoC package as taking over the function of the Logic Board, now that interconnects can be done on the wafer instead.A10x is on TSMC 10nm.
I came across this article from June 2015:Now I want to see the die size normalized for wafer price . In any case x'tor density with those 3.2B ones is astounding. Probably the only piece of the silicon that is not crapped up with SRAM and dense logic are the 2 HP cores.
BTW, the Chipworks iPhone has Intel modem, so congrats to Intel.
Does Intel have an equivalent of InFO?With InFO, the wafer package can mix such that the GPU can be 16nm, the various cores 10nm, etc. Now we will need to wait for the X-Rays to ascertain which part is at which scaling. Unless Apple tells us outright. Typically SRAM is the first to shrink. Look at the SoC package as taking over the function of the Logic Board, now that interconnects can be done on the wafer instead.
BTW, the A10 sure looks a lot like what ARM is doing with HBM2 on their high-end discreet GPUs with regard to the RAM...
http://www.appliedmaterials.com/nan...tions/december-2015/fan-out-is-a-game-changerVardaman said Intel, by virtue of its acquisition of Infineon’s wireless operation, is an early adopter. Intel’s Wireless Division uses fan-out packaging for an LTE multichip part that measures just 5.32 by 5.04 mm.