Apple A9X the new mobile SoC king

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Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
Not that Apple is doing it the same as TI, but before Apple there was TI and it had 80% mobile phone market share. They fabbed the same chip at no less than four companies - 3 foundries plus their own fabs.

The way this was made possible, without making it painfully clear to the consumer that the chip inside one Nokia phone possessed superior electrical parametrics to those of the chip in another phone was by way of locking in electrical specs and then using binning as the variable in the equation.

The way this would work in practice, and I am just crudely speaking to the complexities in this post for the sake of brevity, but let's say you have Foundry A that can technically meet the electrical specs (it is within engineering margin for spice models, leakage, thermals, etc) but only just, meanwhile you have Foundry B that can easily meet the electrical specs because technically your specs (TI's in this case) are designed to allow even the weakest link (foundry) be capable of delivering chips to the packaging house in the Philippines.

So what happens in this simplified situation is that Foundry A struggles and strives to hit parameteric yields for binning your chips. Let's say, for sake of argument, they can deliver 50% yields (parametric and functional) at your required TDP, Tcase, IDDQ, TDDB, etc. Meanwhile Foundry B, with its electrically higher performing process, can deliver 85% yields at your required specs.

What is also true, but no one takes advantage of, is that Foundry B could also deliver superior binned chips with lower TDP, Vdd, IDDQ, etc., albeit at reduced yield (say 50% in this case, iso-yield normalize across the two foundries) if that was of interest to the customer (TI in this real-world example case).

But the customer in this case isn't interested in better-binned but lower yielding chips from Foundry B. They just want volumes and volumes of chips that meet the spec. And the easiest way to hit the spec is to set an operating voltage (and essentially an operating power consumption) for each foundry such that the chips coming to packaging are all operating within the same electrical and thermal profile, even if needlessly so.

In other words, to be sure for TI there were a significant number of chips from Foundry B which were essentially operating in a needlessly overvolted condition with respect to their potential had they been better binned. But had they been optimized for power consumption then it would have simply and needlessly complicated the binning process, raised costs (lower yields or longer validation/test times) and ultimately created the opportunity for customers to realize there were "golden samples" to be had if they endeavored to find them.

I don't know if Apple operates in similar fashion to how TI operated a few years ago in managing multi-sourced ICs, but if they are telling TSMC and Samsung to bin any and all chips as yielding and sellable provided they meet a specific functional clockspeed, thermal, and power target then for sure no one is going to waste time and money figuring out of a certain foundry's subset of chips can operate at the same clockspeed with better thermals or power numbers. That is not something that can be leveraged to compel the consumer to pay more money for the SKU, and it would merely add cost to the supply chain side.
 
Mar 10, 2006
11,715
2,012
126
Not that Apple is doing it the same as TI, but before Apple there was TI and it had 80% mobile phone market share. They fabbed the same chip at no less than four companies - 3 foundries plus their own fabs.

The way this was made possible, without making it painfully clear to the consumer that the chip inside one Nokia phone possessed superior electrical parametrics to those of the chip in another phone was by way of locking in electrical specs and then using binning as the variable in the equation.

The way this would work in practice, and I am just crudely speaking to the complexities in this post for the sake of brevity, but let's say you have Foundry A that can technically meet the electrical specs (it is within engineering margin for spice models, leakage, thermals, etc) but only just, meanwhile you have Foundry B that can easily meet the electrical specs because technically your specs (TI's in this case) are designed to allow even the weakest link (foundry) be capable of delivering chips to the packaging house in the Philippines.

So what happens in this simplified situation is that Foundry A struggles and strives to hit parameteric yields for binning your chips. Let's say, for sake of argument, they can deliver 50% yields (parametric and functional) at your required TDP, Tcase, IDDQ, TDDB, etc. Meanwhile Foundry B, with its electrically higher performing process, can deliver 85% yields at your required specs.

What is also true, but no one takes advantage of, is that Foundry B could also deliver superior binned chips with lower TDP, Vdd, IDDQ, etc., albeit at reduced yield (say 50% in this case, iso-yield normalize across the two foundries) if that was of interest to the customer (TI in this real-world example case).

But the customer in this case isn't interested in better-binned but lower yielding chips from Foundry B. They just want volumes and volumes of chips that meet the spec. And the easiest way to hit the spec is to set an operating voltage (and essentially an operating power consumption) for each foundry such that the chips coming to packaging are all operating within the same electrical and thermal profile, even if needlessly so.

In other words, to be sure for TI there were a significant number of chips from Foundry B which were essentially operating in a needlessly overvolted condition with respect to their potential had they been better binned. But had they been optimized for power consumption then it would have simply and needlessly complicated the binning process, raised costs (lower yields or longer validation/test times) and ultimately created the opportunity for customers to realize there were "golden samples" to be had if they endeavored to find them.

I don't know if Apple operates in similar fashion to how TI operated a few years ago in managing multi-sourced ICs, but if they are telling TSMC and Samsung to bin any and all chips as yielding and sellable provided they meet a specific functional clockspeed, thermal, and power target then for sure no one is going to waste time and money figuring out of a certain foundry's subset of chips can operate at the same clockspeed with better thermals or power numbers. That is not something that can be leveraged to compel the consumer to pay more money for the SKU, and it would merely add cost to the supply chain side.

Makes a lot of sense. Thanks for the insight!
 

StrangerGuy

Diamond Member
May 9, 2004
8,443
124
106
Apple won't give a flying crap to the manufacturing process as long as the chips meets their specifications, volume and cost. Having TSMC as a second source for more chip supply and bargaining power against Samsung are far more critical than process advantage, die size blah blah that are ultimately irrelevant to the end user.
 

Space69

Member
Aug 12, 2014
39
0
66
We build Geekbench with the de-facto standard compiler for each platform since this how most software is built.

Does this include bitcode delivery via Xcode? It's default, but still optional for now - this will be a requirement in the near future. How will you prevent behind the scene optimizations?
 

imported_ats

Senior member
Mar 21, 2008
422
63
86
Only on Apple platforms, though. Other platforms don't have an equivalent to Accelerate.

Why not write to the generic BLAS interfaces and runtime link into the various packages such as MKL/OpenBLAS/Accelerate/ATLAS/etc. Seriously, if you are still gong to test SGEMM/DGEMM performance without using basically standard practice for anyone anywhere doing any SGEMM/DGEMM workload, what's the point? After all, there is a reason that there is a standard BLAS interface and everyone plus their dog has plug in BLAS libraries to support it.

If a platform doesn't have any accelerated support for BLAS, there are generate C libraries that support the interface.
 

imported_ats

Senior member
Mar 21, 2008
422
63
86
For the technology to show impact it must be either:
1) They use different designs (on RTL level)
2) They run at different clock-speeds

I consider both very unlikely.

Um, the odds of the TSMC and Samsung process having the same parametric parameters is basically NIL. That means that the finished designs are going to exhibit different characteristics esp wrt performance changes due to thermal issues.
 

Thanatosis

Member
Aug 16, 2015
102
0
0
They already exhibit different characteristics. The average geekbench for the 6s plus is ~30 points lower on average than the 6s and there is a smaller range of frequencies as cited by Lopri in the iPhone 6s thread in mobile devices and gadgets. It is clear that Apple has used APL1022 in the 6s plus because it is a larger chip and probably also due to the rumored superior power characteristics of TSMC 16nm FF vs Samsung's process.

Every single teardown I have seen has had APL1022 in the 6s plus, and APL0898 in the 6s. The *only* evidence that they are dual sourcing for the "exact same phone" (i.e. both 898 and 1022 in the 6s) is a vague statement from a chipworks release where their own teardown clearly shows APL1022 in the 6s Plus. When they said "otherwise identical" they were referring to the phones having otherwise identical components, the only difference being the size of the device.

Here are the cited teardowns:
https://www.ifixit.com/Teardown/iPhone+6s+Teardown/48170
https://www.ifixit.com/Teardown/iPhone+6s+Plus+Teardown/48171
http://www.chipworks.com/about-chipworks/overview/blog/inside-the-iphone-6s

If we see a teardown of an iphone 6s with APL1022 or and iphone 6s plus with APL0898 then we can conclude that they are dual sourcing for the exact same phone, otherwise all evidence points to two different chips for the iphone 6s and 6s plus. The scores point to it, the teardown points to it, and logic points to it. The only thing that points elsewhere is a vague 20 word chipworks press release, and IDC's already proven-wrong statements about TSMC being the lead supplier for the 6s launch.
 

EightySix Four

Diamond Member
Jul 17, 2004
5,121
49
91
http://demo.hiraku.tw/CPUIdentifier/

Here's the breakdown so far according to a developer who popped up on Reddit with his app. My 6S tested as Samsung. Take it with a grain of salt since it could be a random read out for all we know, but it's better than the nothing information we have thus far. I'm sure if the detection method is legit the benchmark apps will have it integrated soon enough and we'll get some real data.

I wouldn't run this on a phone that you have private information on, you have to add a corporate profile to launch the app since it isn't distributed by the store.
 
Last edited:

paffinity

Member
Jan 25, 2007
89
1
71
Why not write to the generic BLAS interfaces and runtime link into the various packages such as MKL/OpenBLAS/Accelerate/ATLAS/etc. Seriously, if you are still gong to test SGEMM/DGEMM performance without using basically standard practice for anyone anywhere doing any SGEMM/DGEMM workload, what's the point? After all, there is a reason that there is a standard BLAS interface and everyone plus their dog has plug in BLAS libraries to support it.

If a platform doesn't have any accelerated support for BLAS, there are generate C libraries that support the interface.

Yes, I totally agree. The common code argument only goes so far. For well known benchmarks (dhrystone, Spec CPU) compilers will optimize out a lot of the code. Take for example, libquantum in CPU2006.
 

Nothingness

Platinum Member
Jul 3, 2013
2,717
1,347
136
Yes, I totally agree. The common code argument only goes so far. For well known benchmarks (dhrystone, Spec CPU) compilers will optimize out a lot of the code. Take for example, libquantum in CPU2006.
libquantum is the perfect example of compiler over tuning for a benchmark, I'd even call it pure and simple cheating. At the very least, as a benchmark, libquantum is broken.
 
Dec 30, 2004
12,554
2
76
Keep in mind though that even if this statement is accurate, that 15-20% SoC power efficiency advantage would not translate to 15-20% battery life gains. There are other things in the phone that use a lot of power. Like the screen/backlight for instance.

screen and backlight use very little actually. I can get > 10hours screen on time on a static screen on my Nexus 5.

Interacting with the phone is the problem...
 

Eug

Lifer
Mar 11, 2000
23,740
1,274
126
http://demo.hiraku.tw/CPUIdentifier/

Here's the breakdown so far according to a developer who popped up on Reddit with his app. My 6S tested as Samsung. Take it with a grain of salt since it could be a random read out for all we know, but it's better than the nothing information we have thus far. I'm sure if the detection method is legit the benchmark apps will have it integrated soon enough and we'll get some real data.

I wouldn't run this on a phone that you have private information on, you have to add a corporate profile to launch the app since it isn't distributed by the store.
After 2500 units, 59% TSMC 41% Samsung. Not segregated by iPhone size.

And yeah, that makes perfect sense to me. The reasons given in this thread as to why Apple wouldn't do this seem too theoretical to me, but as a layperson, what do I know?
 

coercitiv

Diamond Member
Jan 24, 2014
6,369
12,746
136
After 2500 units, 59% TSMC 41% Samsung. Not segregated by iPhone size.

And yeah, that makes perfect sense to me. The reasons given in this thread as to why Apple wouldn't do this seem too theoretical to me, but as a layperson, what do I know?
At least now we can concentrate on the fun stuff, comparison time! :biggrin:
 

stingerman

Member
Feb 8, 2005
100
11
76
I am still guessing they will bench the same, with throttling not being a significant issue, except under unusual conditions.


Why do so many assume it's better?

TSMC claims their newest version of FinFet produces a transistor that is 10% faster than Samsungs latest FinFet.
 

EightySix Four

Diamond Member
Jul 17, 2004
5,121
49
91
TSMC claims their newest version of FinFet produces a transistor that is 10% faster than Samsungs latest FinFet.

Out of curiosity, would peak switching speed matter in this situation? Wouldn't the electrical characteristics be more interesting between two processors running at the exact same frequency?
 
Last edited:
Mar 10, 2006
11,715
2,012
126
After 2500 units, 59% TSMC 41% Samsung. Not segregated by iPhone size.

And yeah, that makes perfect sense to me. The reasons given in this thread as to why Apple wouldn't do this seem too theoretical to me, but as a layperson, what do I know?

Definitely think some posters here owe IDC an apology.
 

Fjodor2001

Diamond Member
Feb 6, 2010
3,917
395
126
So potentially the Apple customers are participating in a chip lottery? Some will get Samsung chips, some TSMC chips. Both may be clocked at the same frequency, but may e.g throttle differently.

Of course there may be variations between individual chips from the same manufacturer too, but still interesting.

Kind of reminds me of the panel lottery when buying LCD TVs...
 

lopri

Elite Member
Jul 27, 2002
13,211
597
126
After 2500 units, 59% TSMC 41% Samsung. Not segregated by iPhone size.

And yeah, that makes perfect sense to me. The reasons given in this thread as to why Apple wouldn't do this seem too theoretical to me, but as a layperson, what do I know?

Wasn't there a complaint last year because some iPhone 6 were equipped with TLC NAND and some with MLC? I do not think it is theoretical, even if it is unlikely to cause a problem of that scale.

In any case a comparison between the two A9s is going to be interesting.
 
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dark zero

Platinum Member
Jun 2, 2015
2,655
138
106
So potentially the Apple customers are participating in a chip lottery? Some will get Samsung chips, some TSMC chips. Both may be clocked at the same frequency, but may e.g throttle differently.

Of course there may be variations between individual chips from the same manufacturer too, but still interesting.

Kind of reminds me of the panel lottery when buying LCD TVs...

Even Intel Sandy Bridge was a lottery... But the norm was that the chips assembled in Costa Rica were superior chips who reach 5Ghz... And was an abnormal high ammount
Now since some chips are made/assembled in Israel, the quality dropped somehow... However in others fabs (Us or China), the performance is not different compared to previous generations.
 
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