Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[Mopetar]

So are we agreed that the mystery is solved?

And they would have gotten away with it if not for you meddling kids and your Doug!

With apologies to @Doug S

 

[FlameTail]

The die size of the M1 Max is 425 mm², which means they just about could fit two dies into one reticle.

Reticle size: 858 mm²

M1 Max × 2 : 850 mm²

This makes me wonder about the M2 Max. The base M1 -> M2 had a substantial jump in die size, so I assume M2 Max die size also increased.

That means Apple could only fit 1 M2 Max die per reticle! Hence production cost for M2 Max would be substantially higher!

Reason: https://www.semianalysis.com/p/die-...st?utm_source=/search/asml&utm_medium=reader2

The lithography machine would spend more time doing it's thing because per mask shot, it can only do one M2 Max chip, compared to two M1 Max chips per mask shot.

 

[Doug S]

Wasn't it shown that the die size of the M1 Max was actually more like 500 mm^2, since the die photos Apple showed did not include the I/O pads on the bottom that were used to connect two of them together for an M1 Ultra? I would guess that all three Max versions are too big to pair up in a reticle.

Remember that two of them must also fit length/width wise into the 33x26mm reticle, simply being less than 429 mm^2 isn't sufficient to fit two. I don't know the HxL of the Max dies offhand, but I wouldn't be surprised if they're disqualified on that metric as well.

 

[SteinFG]

That means Apple could only fit 1 M2 Max die per reticle! Hence production cost for M2 Max would be substantially higher!

I am not aware of TSMC charging per mask print. They charge by wafer. The only con that smaller mask utilisation makes is slightly slower print time, which TSMC accounts for in their average cost, if I recall correctly.

 

[FlameTail]

I am not aware of TSMC charging per mask print. They charge by wafer. The only con that smaller mask utilisation makes is slightly slower print time,

Hmm. Did you read the semianalysis article I linked?

which TSMC accounts for in their average cost, if I recall correctly.

Average cost? So then the price-per-wafer is not fixed, and varies?

Then what the article is saying is very relevant. More lithography time significantly increase the lithography cost, and in their worst-case-scenarior example, the lithography cost is up by $2000!

 

[FlameTail]

Has anyone measured the core size of A17 P-core?

I did some crude work, and found it to be about 2.2 mm².

 

[gdansk]

Wow, that estimated yield for a ~103mm² part. N3B more like N3Bad

 

[FlameTail]

Also isn't it remarkable how tiny the Neural Engine is?

It takes up about the space of 2 P-cores, so <5 mm².

5 mm² for 18 TOPS of FP16 performance?

 

[mikegg]

5 mm² for 18 TOPS of FP16 performance?

A17 Pro has 35 TOPS. It's the M3 that only has 18 TOPS. For whatever reason, Apple decided to chop it in half for the M3.

 

[FlameTail]

A17 Pro has 35 TOPS. It's the M3 that only has 18 TOPS. For whatever reason, Apple decided to chop it in half for the M3.

35 TOPS INT8?

 

[Doug S]

35 TOPS INT8?

Yeah I'm skeptical of anyone's claims for "TOPS" since there is no standard way of measuring it. It is worse than Drystone MIPS or megahertz as a performance indicator.

 

[DrMrLordX]

Wow, that estimated yield for a ~103mm² part. N3B more like N3Bad

Kinda makes you wonder if N3B's yields will ever get any better.

 

[FlameTail]

Wow, that estimated yield for a ~103mm² part. N3B more like N3Bad

Do you trust the figure in that picture? What's the original source for N3B yield numbers?

 

[Nothingness]

Do you trust the figure in that picture? What's the original source for N3B yield numbers?

TSMC’s 3nm yield rate reportedly just 55% · TechNode

TSMC is struggling with its new 3nm process, with the semiconductor giant's yield rate reportedly far below the standard expected.

technode.com

So it seems to come from wccftech, a very reliable web site. Kidding

 

[FlameTail]

So it seems to come from wccftech, a very reliable web site. Kidding

This forum seriously needs a :skull: reaction

 

[DrMrLordX]

This forum seriously needs a :skull: reaction

Nah it's overused on TikTok and elsewhere.

 

[FlameTail]

Apple M3 die size is 146 mm² (estimate).

Source: https://www.tomshardware.com/softwa...billion-to-tape-out-new-m3-processors-analyst

 

[FlameTail]

Mx -> 1 RAM package
Mx Pro -> 2 RAM packages
Mx Max -> 4 RAM packages

This means each RAM package is connected to a 128 bit bus.

But x128 RAM packages don't exist- atleast that's what I thought after seeing this:


According to Samsung's official website on LPDDR5, they have x32 and x64 'parts'.

Now I am doubtful.

Is it possible to combine two x64 parts to get an x128 package? Is that how it works?

 

[SteinFG]

Mx -> 1 RAM package
Mx Pro -> 2 RAM packages
Mx Max -> 4 RAM packages

Wrong config.
Memory by Micon; plus Apple uses something custom iirc.
M1/M2/M3 - two x64 modules
M1pro - two x128 modules
M2pro - four x64 modules
M3pro - three x64 modules
M1max/M2max/M3max - four x128 modules

 

[FlameTail]

Wrong config.
Memory by Micon; plus Apple uses something custom iirc.
M1/M2/M3 - two x64 modules

By 'modules' you mean dies right?
So two x64 dies bundled into one package.

 

[Glo.]

Mx -> 1 RAM package
Mx Pro -> 2 RAM packages
Mx Max -> 4 RAM packages

This is M1 package.

Does this look like single RAM package?

 

[FlameTail]

This is M1 package.

Does this look like single RAM package?

Uhm.

Very well...

Yeah.

Of course.

How could I misremember!?

 

[Doug S]

Kinda makes you wonder if N3B's yields will ever get any better.

Perhaps not. N3E is basically TSMC's "fixed" N3 and that's where they are trying to push customers. Even to the point that there are rumors that Apple will switch its designs using N3B to N3E. If so, it may be because TSMC's "known good die" deal has an expiration date, and at Apple's volumes the cost of porting from N3B to N3E maybe be less than taking the yield hit at per wafer pricing. Or perhaps as part of the KGD deal to keep Apple happy they also agreed to fund the port to N3E. So whether N3B's yields improve may be irrelevant to Apple.

The wildcard in this is Intel. It is still claimed they will be using N3B for the N3 chiplets they are sourcing from TSMC, despite sufficient time for them to have ported to N3E. But there are a lot of variables such as available N3E capacity, terms of their deal with TSMC, etc. Heck maybe the plan is to get Apple on N3E and then Intel essentially takes over the N3B capacity Apple was using. TSMC may have less incentive to improve yields if Intel is the only one using N3B, given that Intel will become a major foundry competitor and is unlikely to ever use TSMC capacity to such a degree (and even if they are unhappy and in the future need more capacity than they have themselves, their only alternative is Samsung)

 

[FlameTail]

.The wildcard in this is Intel. It is still claimed they will be using N3B for the N3 chiplets they are sourcing from TSMC, despite sufficient time for them to have ported to N3E. But there are a lot of variables such as available N3E capacity, terms of their deal with TSMC, etc. Heck maybe the plan is to get Apple on N3E and then Intel essentially takes over the N3B capacity Apple was using. TSMC may have less incentive to improve yields if Intel is the only one using N3B, given that Intel will become a major foundry competitor and is unlikely to ever use TSMC capacity to such a degree (and even if they are unhappy and in the future need more capacity than they have themselves, their only alternative is Samsung)

Yaya N3E is better but if everyone moves to N3E, then what becomes of the N3B production lines? Are they going to just sit and rot? Which is why I think TSMC would be incentivised to have Intel using N3B.

 

[DrMrLordX]

The wildcard in this is Intel. It is still claimed they will be using N3B for the N3 chiplets they are sourcing from TSMC, despite sufficient time for them to have ported to N3E. But there are a lot of variables such as available N3E capacity, terms of their deal with TSMC, etc. Heck maybe the plan is to get Apple on N3E and then Intel essentially takes over the N3B capacity Apple was using. TSMC may have less incentive to improve yields if Intel is the only one using N3B, given that Intel will become a major foundry competitor and is unlikely to ever use TSMC capacity to such a degree (and even if they are unhappy and in the future need more capacity than they have themselves, their only alternative is Samsung)

That's why I asked about it in the first place. With yields like that, it's a bit concerning that Intel would finally start taking N3B wafers.