Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

Page 78 - Discussion - Apple Silicon SoC thread

Page 78 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M1 Ultra discussion here:

Page 109 - Discussion - Apple Silicon SoC thread

Page 109 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M2 discussion here:

Page 127 - Discussion - Apple Silicon SoC thread

Page 127 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

Page 215 - Discussion - Apple Silicon SoC thread

Page 215 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M4 Family discussion here:

Page 263 - Discussion - Apple Silicon SoC thread

Page 263 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[adroc_thurston]

Any other chips have SME?

no

Qualcomm and Mediatek?

QC doesn't even have SVE(1).

 

[adroc_thurston]

Also this is not like the Skylake era like I seen some people on Twitter saying it is.

It's worse, yea, Intel managed to milk v/f improvements from the same node.

Unlike Intel, Apple is not staying on the same node.

yeah that's the issue, they're just shrinks.

I want the same response for Zen 5, if the some of IPC improvements come from improved AVX512 support then people should also deduct IPC.

The relevant Z5 numbers are not AVX-512.
Why the cope?

They did increase L1 latency slightly it seems with M4?

M3.
Dem Mhz aren't free fellas.

 

[gdansk]

It's worse, yea, Intel managed to milk v/f improvements from the same node.

Don't give Intel any kudos for that. It was almost entirely through ignoring power. This is not a luxury the Apple tablet/MBA SoC has with their hatred of fans (and I appreciate it).

 

[adroc_thurston]

It was almost entirely through ignoring power

nope, try the 4c comet-u and compare the v/f to KBL-R the OG.

 

[poke01]

Why the cope?

Yeah, you are right. Apple better get their act together. It’s looking unlikely though.

That means they have to win people with software but they are behind that too. WWDC 24 is make or break.

 

[poke01]

no

QC doesn't even have SVE(1).

Interesting. So Apple is the first to implement SME on devices.

Crazy when Cortex X4 already supports it.

 

[adroc_thurston]

So Apple is the first to implement SME on devices.

yea.
not that it matters.

Crazy when Cortex X4 already supports it.

QC committed to shipping Nuvia cores everywhere which is a pickle, they're iirc v8.5 without SVE.

 

[Doug S]

Yeah Doug I agree mostly. I think two caveats are in order:
They did increase L1 latency slightly it seems with M4? But that’s it. Don’t think they’re doing any major restructuring.

That was M3 (at least that's what I saw reported, I never saw a link to an actual source for that claim)

Nevertheless, increasing L1 latency is not in any way equivalent to increasing pipe stages. There are plenty of reasons you might increase cache latency that have nothing to do with operating at a higher clock rate: you're making it bigger, you're increasing the number of ways, you're using different transistor layouts, or (Apple's favorite) you're reducing its power consumption. The trick is, can you make up for that extra cycle in some way so it doesn't regress performance in some types of code?

 

[adroc_thurston]

you're making it bigger, you're increasing the number of ways, you're using different transistor layouts, or (Apple's favorite) you're reducing its power consumption

well no, L1 macro tends to be a big speed limit in many places.

The trick is, can you make up for that extra cycle in some way so it doesn't regress performance in some types of code?

they did in fact not.

 

[gdansk]

They increased clock rate 25% and also L1 cycles by 25% over 2 years. It may (possibly!) be related. But it's the same access time isn't it?
Also they must have made changes elsewhere to compensate. IPC isn't dropping. Apple says power isn't increasing. Pursuing high clock rate is a good thing. If they can do it more quickly than massive redesigns for more IPC I can see why they'd prefer it.

Edit: adroc says increase from 3->4. I thought it was 4->5.

 

[SpudLobby]

Apple says power isn't increasing.

They said they have more power gains vs M2 than they stated for the M3 - specifically 50% or whatever — but in MT, which is enabled in part by 2 more E Cores and an extra - 10% power from N3E (over N3B). They already had like 20-30% or whatever from the M3 over the M2, to be clear. I forget the metrics but I’d bet power for the P core is up just slightly at minimum (which would be impressive if slight).

Basically they didn’t say anything about the individual cores.

I doubt the P Core is using that much power grand scheme and relative to AMD (N4P) or Lunar Lake (N3B Intel just sucks) it will blow them out of the water given they’re using this in a fanless tablet and well, it’s N3E and Apple. The curve will blow QC on N4P out too just to a lesser extent.

But the trajectory for Apple is not great even if their products still lay waste to everyone else in at least some ways still today. They used to be ahead by not only more but in two qualitative vectors. They’re riding off a very efficient and high IPC foundation and the latter is being eroded, the former less so, but we’ll see with 8 Gen 4 & D9400’s X5 on N3E etc.

 

[adroc_thurston]

IPC isn't dropping

it did drop in specint rofl.

Edit: adroc says increase from 3->4.

yeah 33% moar cycles. stinks.

 

[poke01]

Let’s wait for Geekerwan. But things aren’t looking good

 

[poke01]

For a while, Apple has been sending out review units to Geekerwan and their analysis is good.

Hopefully by next week.

 

[poke01]

But the trajectory for Apple is not great even if their products still lay waste to everyone else in at least some ways still today. They used to be ahead by not only more but in two qualitative vectors. They’re riding off a very efficient and high IPC foundation and the latter is being eroded, the former less so, but we’ll see with 8 Gen 4 & D9400’s X5 on N3E etc.

That’s the thing, they can’t forever keep on increasing clocks without IPC improvements in the double digits.

Apple loves to make things thin and fanless and they can’t do that if their chips stall.

 

[Nothingness]

I find AVX 512's flexibility to operate on data types larger than 16 bits make it more applicable than SME. It's more akin to SVE (which no one is deducting?).

Yeah, AVX should not be compared with SME, but with SVE. SME should be compared with Intel AMX, and it looks like AMX only supports BF16 and FP8.

 

[Ajay]

Yeah, you are right. Apple better get their act together. It’s looking unlikely though.

That means they have to win people with software but they are behind that too. WWDC 24 is make or break.

I don't think WWDC 24 is make or break. Apple's priorities have been Services, Walled garden, incremental software improvements and incremental hardware improvements approx in that order. They have been doubling down on security - in part as a means to strength the Apple ecosystem (at least in the minds of consumers). I think the biggest area of threat to them is Walled garden - we'll have to see how that plays out. Services is a very competitive market. Apple will need to become more agile to maintain its sales and profits. Apple is, and will continue to lose share in China due to rising anti-americanism which is strengthened by Apple moving production out of China to other Asian countries and India.

 

[SarahKerrigan]

Lot of extremes in this thread and elsewhere - either M4 is the most amazing thing ever or doomed Apple.

It seems to me like the truth is somewhere in the middle - that the M4 is a decent rev of the M3 architecture with some nice freebies (SME, two additional small cores) and a small clock bump from the jump to N3E. Considering it's only a few months later than M3 was, that does not seem like a horrible thing necessarily. On the other hand, folks proclaiming loudly that Apple is back to massive inter-generational bumps seem to be putting a lot of weight in one, rather specialized, feature, which is good at blowing out one subtest of one benchmark but likely will not work miracles on most random code streams.

Intel (VNNI, AMX, QuickAssist) and IBM (decimal FP, Power10 matrix ops) have been doing the "look how fast it goes when you hit the exact thing that we built a big specialized accelerator for" game for a while, and while it's nice to have, it's not the same thing as a large general-purpose cross-generation improvement.

 

[Eug]

Seems those Geekbench 6 numbers are consistent. Here is a new bench:

3823 single-core / 14749 multi-core

 

[Mopetar]

It doesn't have to be a completely new core to be a good SoC. Sometimes patching up what you have and making a few changes or worthwhile additions are fine.

One concern I have is battery life. I don't think Apple talked about it, but they did mention how thin this new iPad is going to be and that of course means a smaller battery.

Maybe their new OLED screen is incredibly efficient and means that's not a worry, but I'd like to see some performance reviews.

 

[Eug]

One concern I have is battery life. I don't think Apple talked about it, but they did mention how thin this new iPad is going to be and that of course means a smaller battery.

Maybe their new OLED screen is incredibly efficient and means that's not a worry, but I'd like to see some performance reviews.

OLED and two extra efficiency cores too. BTW, supposedly dual-stack / tandem OLED uses less power than single layer OLED, at least at higher brightness that is.

The 13" iPad Pro does indeed have a slightly smaller battery, down 4.6% to 38.99 Whr, from 40.88 Whr.
However, the 11" iPad Pro has an 8.2% bigger battery. It's now 31.29 Whr (vs 28.93 Whr).

 

[poke01]

It doesn't have to be a completely new core to be a good SoC. Sometimes patching up what you have and making a few changes or worthwhile additions are fine.

One concern I have is battery life. I don't think Apple talked about it, but they did mention how thin this new iPad is going to be and that of course means a smaller battery.

Maybe their new OLED screen is incredibly efficient and means that's not a worry, but I'd like to see some performance reviews.

The 11-inch ‌iPad Pro‌ has a 31.29-watt-hour battery, up from 28.65‐watt‐hours in the prior-generation model, while the 13-inch ‌iPad Pro‌ has a 38.99-watt-hour battery, down from 40.88-watt-hours.

From Macrumours.

 

[poke01]

I don't think WWDC 24 is make or break. Apple's priorities have been Services, Walled garden, incremental software improvements and incremental hardware improvements approx in that order. They have been doubling down on security - in part as a means to strength the Apple ecosystem (at least in the minds of consumers). I think the biggest area of threat to them is Walled garden - we'll have to see how that plays out. Services is a very competitive market. Apple will need to become more agile to maintain its sales and profits. Apple is, and will continue to lose share in China due to rising anti-americanism which is strengthened by Apple moving production out of China to other Asian countries and India.

IMO, this year is an important year for Apple’s software which has largely been the same since 2010.

Apple’s executives see A.I has a threat to the iPhone market share. iOS is behind in many ways. They cannot do incremental updates this year for software.

 

[poke01]

Lot of extremes in this thread and elsewhere - either M4 is the most amazing thing ever or doomed Apple.

It seems to me like the truth is somewhere in the middle - that the M4 is a decent rev of the M3 architecture with some nice freebies (SME, two additional small cores) and a small clock bump from the jump to N3E. Considering it's only a few months later than M3 was, that does not seem like a horrible thing necessarily. On the other hand, folks proclaiming loudly that Apple is back to massive inter-generational bumps seem to be putting a lot of weight in one, rather specialized, feature, which is good at blowing out one subtest of one benchmark but likely will not work miracles on most random code streams.

Intel (VNNI, AMX, QuickAssist) and IBM (decimal FP, Power10 matrix ops) have been doing the "look how fast it goes when you hit the exact thing that we built a big specialized accelerator for" game for a while, and while it's nice to have, it's not the same thing as a large general-purpose cross-generation improvement.

well said. There is always turmoil whenever Apple does something.

 

[Ajay]

IMO, this year is an important year for Apple’s software which has largely been the same since 2010.

Apple’s executives see A.I has a threat to the iPhone market share. iOS is behind in many ways. They cannot do incremental updates this year for software.

Well, for consumer products, even PCs, AI is a 'sticker' item. Slap the term AI on it and buyers will be happy that they have the latest bit. As Apple can define AI as they wish - they can do it anytime - IMHO. Of course, compared to google/android - Siri is a dunce anyway; and yet Apple buyers do not seem to care**. That said - Apple still needs to work hard on their backend, it’s a long term problem that could limit their market share if people really start to care.

Anyway, that’s my opinion - we'll see what Apple really thinks at WWDC this summer.

**I'm a long term iPhone user and I rarely use Siri, because it’s still not much more helpful than looking things up myself on the web, but it’s no deal breaker for me.