Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[SpudLobby]

The people saying that are probably all for AVX512 counting in benchmarks despite ARM CPUs having only 128 bit wide NEON making for an unfair comparison where SIMD resources dominate.

If you don't like all that extra stuff, just look at clang results and ignore the rest. New instructions are not going to speed up clang/gcc, bigger caches and higher clock rates on their own don't have a lot of impact. If you want a way to compare progress on CPUs that's unaffected by architectural changes aside from increases in basic wheels on the ground performance, that's how you do it.

Yeah basically

 

[Orfosaurio]

Ha SME 😀 That alone might explain some of the tests huge speedup.

And Intel and AMD have AVX, since before the M family even launched.

 

[adroc_thurston]

And Intel and AMD have AVX, since before the M family even launched.

that's proper SIMD. very different things.

 

[Orfosaurio]

I think at this point I have to say GB6 is no longer a good benchmark.

It should have been called GB7 if something as important as SME was added. It skews the results.

I'm waiting for more workloads but nice to see Apple include SME.

What? Without SME support, the benchmark would be biased against Apple because AMD and Intel have similar instructions. And things like SME are increasingly important because of the AI revolution.

 

[adroc_thurston]

Without SME support, the benchmark would be unfair to Apple because AMD and Intel have similar instructions

No, you're comparing cluster-level matrix math accelerator with proper SIMD.
Don't.

 

[Orfosaurio]

well said. There is always turmoil whenever Apple does something.

It is the Apple, what do you expect?

 

[Orfosaurio]

It’s gonna be sooooo smooth watching Netflix and surfing AnandTech on this tablet.

Maybe not, Apple software has been, at this point, for many years, badly optimized. At least they optimize it along the iterations of the OSs, that's why peak performance and energy efficiency increase along newer versions of their OSs.

 

[Orfosaurio]

No, you're comparing cluster-level matrix math accelerator with proper SIMD.
Don't.

Isn't SME more than a "cluster-level matrix math accelerator"?

 

[adroc_thurston]

Isn't SME more than a "cluster-level matrix math accelerator"?

It's just an ISA-standard AMX replacement.

 

[Nothingness]

It's just an ISA-standard AMX replacement.

Agree. Though it comes with Streaming SVE. But the latter is mostly useless given its performance against NEON in M4 (it seems to be a single 512-bit pipe - perhaps 2x256 - running at the much lower frequency of the SME block, vs 4 128-bit NEON pipes *per core* at a higher freq). Its use will be only to do some vector computations between matrix operations without having to switch between a core and the SME unit.

 

[adroc_thurston]

(it seems to be a single 512-bit pipe - perhaps 2x256 - running at the much lower frequency of the SME block, vs 4 128-bit NEON pipes *per core* at a higher freq)

Throughput is poo, yes.
Latency is worse than poo, though. Garbage.

SME is aight though, free DGEMM for those who need it (nerds).

 

[Eug]

Gurman's M4 release date predictions already seem to be a bit fluid.

Now he is saying that M4 will come around the end of 2024, but only in the 14" MacBook Pro and 24" iMac, and NOT the MacBook Airs.

For M4 Pro/Max MacBook Pros, he states they will come end of 2024/early 2025.

He also suggests M3 Ultra has been shelved. Next Mac Studio could be M4 based in mid 2025, and next Mac Pro could be M4 Ultra in the second half of 2025.

Even after the recent M4 iPad Pro launch, Gurman's M4 series Mac release timeline prediction from mid-April 2024 remains unchanged:

2024 Q4            M4 MacBook Pro
2024 Q4            M4 iMac
2024 Q4/2025 Q1    M4 & M4 Pro Mac mini
2024 Q4/2025 Q1    M4 Pro & Max MacBook Pro
2025 Q2            M4 MacBook Air
2025 Q2/Q3         M4 Max & M4 Ultra Mac Studio
2025 Q2/Q3         M4 Ultra Mac Pro

ie. There will be no Mac announcement at WWDC.

 

[poke01]

There will be no Mac announcement at WWDC.

I’ll

Even after the recent M4 iPad Pro launch, Gurman's M4 series Mac release timeline prediction from mid-April 2024 remains unchanged:

2024 Q4            M4 MacBook Pro
2024 Q4            M4 iMac
2024 Q4/2025 Q1    M4 & M4 Pro Mac mini
2024 Q4/2025 Q1    M4 Pro & Max MacBook Pro
2025 Q2            M4 MacBook Air
2025 Q2/Q3         M4 Max & M4 Ultra Mac Studio
2025 Q2/Q3         M4 Ultra Mac Pro

ie. There will be no Mac announcement at WWDC.

thats not rapid at all. If it was a quick move to M4, the base M4 needs to come out at WWDC for Mac mini. Gurman can be wrong.

 

[Eug]

thats not rapid at all. If it was a quick move to M4, the base M4 needs to come out at WWDC for Mac mini. Gurman can be wrong.

Yeah, he could be wrong of course, but I just find it interesting his predicted timeline hasn't changed since the M4 iPad Pro launch. This is in contrast to a lot of people (maybe including yourself?) who are now saying WWDC is going to be a Mac event.

I personally am still inclined to believe Gurman's late 2024 prediction, but I'm biased because before the M4 iPP launch I personally was also predicting late 2024 / early 2025 for M4 Macs. (Basically my prediction was similar to Gurman's, except with some of my release date predictions maybe a couple of months later than his.)

 

[name99]

Agree. Though it comes with Streaming SVE. But the latter is mostly useless given its performance against NEON in M4 (it seems to be a single 512-bit pipe - perhaps 2x256 - running at the much lower frequency of the SME block, vs 4 128-bit NEON pipes *per core* at a higher freq). Its use will be only to do some vector computations between matrix operations without having to switch between a core and the SME unit.

Dude, wait for the people who know what's going before making ideologically based comments.

The initial SSVE results are in fact way too low.

Accumulating to a Z register rather than a ZA register is apparently allowed (terrible footgun by ARM there, allowing that – how long till the compiler/assembler is warning "is this what you really want?")but doe right the instructions run as fast as expected: 250FP32 GFLOPs, with the ability to hit 2000 GFLOPs with the correct ordering and with quad-vector usage.

Real World Technologies - Forums - Thread: Apple and AI

www.realworldtech.com

This was not a surprise. We KNOW how the vector instructions work in AMX. We KNOW that two of them can be packed into a single transaction. (so two vector ops per cycle). We KNOW that they can operate 4-wide (so 8 vector ops per cycle).

All that was required was waiting till some of the people who understand this model get their hands on hardware, rather than simply trusting clearly terrible results from people who clearly don't understand the hardware model.

So the vector ops are not in fact useless. For certain purposes, like long dots, or FFT, they are in fact quite valuable...

My biggest complaint with AMX as it was is that it did not provide great support for complex vectors and matrices. Yeah, you could fake it, but you couldn't hit the full throughput you deserved.
My GUESS is that ARM has forced that into the spec, but I honestly don't know; it will take all of use a few months to read everything that's there, think about it, and realize what might be missing.

Once that's done, next step is HW support for various symmetric and sparse matrices...

 

[Nothingness]

Dude, wait for the people who know what's going before making ideologically based comments.

The initial SSVE results are in fact way too low.

Accumulating to a Z register rather than a ZA register is apparently allowed (terrible footgun by ARM there, allowing that – how long till the compiler/assembler is warning "is this what you really want?")but doe right the instructions run as fast as expected: 250FP32 GFLOPs, with the ability to hit 2000 GFLOPs with the correct ordering and with quad-vector usage.

Maynard, you have no clue what you are talking about. Go read about SVE and SME. ZA is a set of tiles (matrices), while Z are wider registers (vectors). Learn before making silly guesses, dude.

BTW I did discuss with the guys who made the program and analysis of the Apple SME block. I asked them to redo their runs zeroing Z registers (which is not really mandated after SMSTART but that was worth trying as it's trivial); same result: SSVE is 1/64th the speed of SME and much slower than plain NEON. I'm still not 100% sure it is the definitive answer, that's why I wrote "it seems". I'm not enough full of myself, as you sometimes are, to draw conclusions.

I also read about SVE and SME, going as far as implementing a simulator. So feel free to lecture me, it's funny.

 

[carancho]

Pretty much this. I did scrape a few thousands results some years ago, and it was a drag. Luckily, they've you the possibility to access results as neatly formatted JSON, but you need to login to do that, which makes it hard to automate. I'd probably need to write a browser extension for this. If I ever find time.

What's needed is an appropriate sampling methodologyn to scrap only a few 100s or 1000s of results, not scraping the whole database.

Btw, that's likely a very lucrative business for them - doing research of laptop and parts vendors.

 

[Eug]

Weird.

An eagle-eyed MacRumors member has been scanning the videos of all the M4 iPad Pro teardowns, and looking at the DRAM chips.

All of them are 2 chips:
The 1 TB model has 2 x Micron D8DNV = 2 x 8 GB = 16 GB
However, the 256 GB model has 2 x Micron Z8DMS = 2 x 6 GB = 12 GB

Or so it seems at least. Hmmm...

I looked at the images closely and do agree s/he has the name right, and according to online databases, Z8DMS does indeed correspond to a 48 Gigabit part.

Apple only advertises 8 GB so there is no false advertising, but it does seem odd.

However, if true, I think it does make it more likely that the next MacBook Air in 2025 (?) could FINALLY be 12 GB base.

 

[Mopetar]

That's weird. Is it maybe an 11" vs 13" difference? Otherwise that doesn't make much sense to have 6 GB chips. I can't see Apple fusing off 4 GB of RAM either instead of just buying 4 GB chips.

 

[Eug]

That's weird. Is it maybe an 11" vs 13" difference? Otherwise that doesn't make much sense to have 6 GB chips. I can't see Apple fusing off 4 GB of RAM either instead of just buying 4 GB chips.

Well, the Z8DMS naming does check out:

 

[poke01]

We won’t know till M4 MacBooks come out. If those the have same ID but have 12GB ram then Apple is locking out the 4GB of ram on the iPad.

 

[Mopetar]

We won’t know till M4 MacBooks come out. If those the have same ID but have 12GB ram then Apple is locking out the 4GB of ram on the iPad.

They'd have to know that someone would figure that out. The bad press they'd get isn't worth doing something like that solely to differentiate the high and low-end models.

 

[poke01]

They'd have to know that someone would figure that out. The bad press they'd get isn't worth doing something like that solely to differentiate the high and low-end models.

This wouldn’t cause that much of outrage. Apple is advertising 8GB.

My guess would be that if Apple locked the 4GB then it would due to the M3 MacBook Pro having 8GB.

Kinda embarrassing if a $999 tablet has more ram than a $1599 MacBook.

 

[Eug]

This wouldn’t cause that much of outrage. Apple is advertising 8GB.

My guess would be that if Apple locked the 4GB then it would due to the M3 MacBook Pro having 8GB.

Kinda embarrassing if a $999 tablet has more ram than a $1599 MacBook.

That was my thought. M3 MacBook Air and M3 MacBook Pro both start with 8 GB RAM.

Also isn’t it LPDDR5X vs. LPDDR5?

BTW, M4 (or M5 at the latest) and not M3 was when I was predicting the MacBook would start at 12 GB. That wasn’t based on any info, just that it was about time.

 

[Glo.]

Weird.

An eagle-eyed MacRumors member has been scanning the videos of all the M4 iPad Pro teardowns, and looking at the DRAM chips.

All of them are 2 chips:
The 1 TB model has 2 x Micron D8DNV = 2 x 8 GB = 16 GB
However, the 256 GB model has 2 x Micron Z8DMS = 2 x 6 GB = 12 GB

Or so it seems at least. Hmmm...

I looked at the images closely and do agree s/he has the name right, and according to online databases, Z8DMS does indeed correspond to a 48 Gigabit part.

Apple only advertises 8 GB so there is no false advertising, but it does seem odd.

However, if true, I think it does make it more likely that the next MacBook Air in 2025 (?) could FINALLY be 12 GB base.

It means that Apple artificially is limiting the memory in the iPad to 8 GB, out of 12.

How they partition it - no idea.

But that is just ... disgrace by Apple.