Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[jpiniero]

Do you have a summary of the financial report? I came across this article:

https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2023-04/a8e8d45848f7d71c82fb3afcd447c0c29c9fcfb6/TSMC%201Q23%20Transcript.pdf

 

[Eug]

https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2023-04/a8e8d45848f7d71c82fb3afcd447c0c29c9fcfb6/TSMC%201Q23%20Transcript.pdf

That's great, thanks. This is the full quote:

Next, let me talk about our N3 and N3E status. Our 3-nanometer technology is the first in the semiconductor industry to high-volume production with good yield. As our customers' demand for N3 exceeds our ability to supply, we expect N3 to be fully utilized in 2023, supported by both HPC and smartphone applications. Sizable N3 revenue contribution is expected to start in third quarter and N3 will contribute mid-single-digit percentage of our total wafer revenue in 2023.

N3E will further extend our N3 family with enhanced performance, power and yield and offer complete platform support for both HPC and smartphone applications. N3E has passed the qualification and achieve performance and yield targets, and volume production is scheduled for second half '23. Despite the ongoing inventory correction, we continue to observe a high level of customer engagement at both N3 and N3E with the number of tape-outs more than 2x that of N5 in the first and second half year -- in the second year, I'm sorry.

So yes I agree, N3E sounds too late for A17. However, I'm still wondering in if N3 might be a decent possibility for A17 because:

1. A17 will likely only be used in the iPhone Pro line this year, reducing the number of chips needed vs. say A15.

2. They could start high volume production in Q2 and deliver in July 2023 for "sizeable Q3 revenue", which would give them enough time for a September iPhone release. And even if the 2 months until September is too tight, they could release early October. (I've read before that chip availability to significant stock of devices on shelves is realistically ~2 months.)

 

[Doug S]

I still think Apple won't use the 'standard' N3 which is known to have some issues, and they've got a custom version of N3 they'll be using that will likely incorporate some elements of N3E. TSMC would not be announcing the timeline for mass production of a customer specific process so the talk about when N3E is ready for mass production may be irrelevant to Apple.

Revenue is recognized when finished chips are shipped, which Apple doesn't need to happen until Q3 (i.e. after July 1) for a mid September launch. If Apple is the only customer taking N3 deliveries in 2023 (and only using it for half their iPhone 15s to boot) then you can't expect double digit revenue contribution for maybe 50 million chips including M3 Macs this calendar year.

Obviously A17 is using N3, we'll have to wait and see exactly what that 'N3' is but that's academic from TSMC's perspective. If it wasn't then TSMC could never get close to mid single digit revenue contribution this year.

 

[A///]

isn't tsmc winding down their base n3 because of the issues they solved in later variants? I do remember a taiwan times paper translation stating that even tsmc was aware of the poor performance base n3 had.

 

[moinmoin]

Something to keep in mind (and most here keep hinting at already) is that nodes at TSMC are not as clear cut as it's made seem. What TSMC essentially advertises publicly is for what TSMC seeks additional customers. Existing big customers like Apple, MediaTek and AMD etc. that command big volumes work closer with TSMC anyway so the nodes they use can become more of a mix of everything and possibly include changes that TSMC only later makes public as part of a newer node. Strict comparison of node timelines and features with such bigger customers become patchy as a result.

 

[Eug]

OK, A17 on Apple's own flavour of N3B. Got it.

Is it safe to assume that if A17 is Apple N3B, then M3 is also likely Apple N3B?

 

[Ajay]

OK, A17 on Apple's own flavour of N3B. Got it.

Is it safe to assume that if A17 is Apple N3B, then M3 is also likely Apple N3B?

Yes, that is what I've read. N3B - so TSMC tweaked it to optimize it for whatever Apple wanted. Which they normally do anyway.

 

[Doug S]

OK, A17 on Apple's own flavour of N3B. Got it.

Is it safe to assume that if A17 is Apple N3B, then M3 is also likely Apple N3B?

100% certain IMHO.

For both the M1 (using A14 cores) and M2 (using A15 cores) the process of the iPhone SoC matched the process for the Apple Silicon CPU bearing its cores. That saves a fair amount of engineering effort that would be consumed if e.g. A17 and M3 shared the same core but used different processes.

 

[Doug S]

Some relevant stuff in this EEtimes article.

They claim Apple will be paying for "known good chips" with N3, which is a departure from previous nodes where they paid per wafer.

 

[Ajay]

Some relevant stuff in this EEtimes article.

They claim Apple will be paying for "known good chips" with N3, which is a departure from previous nodes where they paid per wafer.

From that article:

Sizable N3 revenue contribution is expected to start in the third quarter, and N3 will contribute a mid-single–digit percentage of our total wafer revenue in 2023

3rd quarter?? Guess N3B will be limited to iPhone Pro models only for A17.

 

[jpiniero]

2. They could start high volume production in Q2 and deliver in July 2023 for "sizeable Q3 revenue", which would give them enough time for a September iPhone release. And even if the 2 months until September is too tight, they could release early October. (I've read before that chip availability to significant stock of devices on shelves is realistically ~2 months.)

For normal products, yes, 2 months is reasonable. But not iPhone.

3rd quarter?? Guess N3B will be limited to iPhone Pro models only for A17.

Now they could limit A17 to just Pro (or even "Pro Max") and release that whenever.

 

[Doug S]

From that article:

3rd quarter?? Guess N3B will be limited to iPhone Pro models only for A17.

Note that it says mid single digit of total 2023 revenue. So with zero contribution in H1, the contribution has to be 10% in H2 to equal 5% for the whole year.

It is probably a safe bet that A17 will be in Pro models only, given that they did that with A16. There was zero cost savings holding back A16 in non Pro phones, but savings in LPDDR5 vs LPDDR4x. They won't have that memory savings this time around (unless they go with LPDDR5X for A17, but I see that as unlikely) but the cost savings this time will be the N3 based A17 vs the N4 based A16. Next year both will be on N3 so maybe they adopt LPDDR5X and that's the cost separation...

 

[Eug]

This is AnandTech’s / Anton Shilov’s article on TSMC process generations, including TSMC’s new info on N2.

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

www.anandtech.com

”Volume Manufacturing” is listed as Q2/Q3 (not just Q3) 2023 for N3E and H2 2025 for N2.

 

[Roland00Address]

I am not confident with future nodes being on time and high volume, TSMC has excess capacity which is a good and bad thing 🥶

TSMC’s Heroic Assumption – Low Utilization Rates, Fab Cancellation, 3nm Volumes, Automotive Weakness, AI Advanced Packaging Demands, 2024 Capex Weakness

Can these heroic assumptions be supported? Tremendous risk.

www.semianalysis.com

 

[repoman27]

If you pay attention to what TSMC is actually saying in their public statements, you'll find much better indicators of Apple's future product plans than you'll be able to glean from the coverage by most media outlets and "analysts".

N3 entered volume production in December 2022. As of the April 20, 2023 earnings call, N3E volume production is still scheduled for H2'23. TSMC has consistently said that N3E volume production was scheduled for around one year after N3. When asked about the timing during the October 13, 2022 earnings call, C.C. Wei indicated that N3E might be pulled in two or three months, which would put it in the September to October 2023 range. So late Q3 would be optimistic, and Q2 was never on the table. Due to cycle times / time to market, no products based on N3E chips will hit the shelves in 2023.

At this point there is only one N3 customer, and that customer is Apple. US trade restrictions are limiting Chinese access to the new node, and Intel couldn't get their act together (if they ever intended to utilize N3 in the first place). TSMC's other customers are declining to pay the premium for early access and are all content to sit back and wait a year for the less complex, less expensive N3E. However, TSMC also reports in their most recent earnings call that demand for N3 exceeds their ability to supply, and that they expect N3 to be fully utilized in 2023, supported by both HPC and smartphone applications.

Therefore Apple is using TSMC N3 for the A17 and M3. And given TSMC's revenue projections, the A17 will likely be used in all of the iPhone 15 models this year. The iPhone launch will almost certainly be in September, and the A17 ramp is already well underway. Normally, TSMC begins the A-series ramp in the March to April timeframe, but due to longer cycle times, capacity constraints, and the need to de-risk the ramp of a brand new process family, they began production earlier this year. TSMC won't recognize revenue for those chips until Apple pays them though, which generally doesn't happen until after the product is delivered. This is why TSMC tells us to expect sizable N3 revenue contribution to start in Q3'23.

TSMC may refer to N3 as "N3B" internally, but publicly they always call it "N3". N3 itself is a stub node, and the rest of the N3 process family will be based on N3E. Given that they went all in on N3, I don't expect Apple to use N3E at all. I reckon the N3S node, which TSMC has been rather tight-lipped about, will be another de facto Apple exclusive node to bridge them back into the broader process family. I'm guessing Apple is going to take the optical shrink from N3P early, and N3S is essentially N3E with a 4% optical shrink and the possible addition of a higher density SRAM bitcell.

And here's an updated table with the relevant comparisons:

	N5P vs N5	N4 vs N5P	N3 vs N4	N4P vs N4	N3E vs N3	N3S vs N3*	N3P vs N3E	N2 vs N3P
Logic Density	same​	1.06x​	1.6x​	same​	0.94x​	0.98x​	1.04x​	>1.11x​
SRAM Density	same​	1.06x​	0.99~1.13x​	same​	0.83~0.95x​	0.87~0.99x​	1.04x​
Speed at Same Power	+5%​	same​	+5~10%​	+6%​	+5%​	+5%​	+5%​	+5~10%​
Power at Same Speed	-15%​	same​	-13~18%​	-9%​	-7%​	-7%​	-5~10%​	-22%​
Product Tape-out				H2'22​
Risk Production	Q2'20​	Q3'21​	Q4'21​		Q4'22​
Volume Production	H1'21​	H1'22​	H2'22 (Dec)​	H1'23?​	H2'23 (Sep~Oct)​	H1'24 (Mar~Apr)​	H2'24​	2025​

*PPA numbers for N3S are purely speculative.

 

[Doug S]

Based on those (speculative) numbers N3S is worse than N3E in logic and SRAM density and therefore cost. So why would Apple choose N3S over N3E for 2024 production?

 

[repoman27]

Based on those (speculative) numbers N3S is worse than N3E in logic and SRAM density and therefore cost. So why would Apple choose N3S over N3E for 2024 production?

Bigger numbers are better.

 

[Ajay]

Bigger numbers are better.

Uh, what bigger numbers??

 

[repoman27]

Uh, what bigger numbers??

0.98x is bigger than 0.94x. N3E is a regression from N3 at 0.94x or 94% of N3's logic density. N3E with a a 4% optical shrink would be 0.94 / 0.96 = 0.98x, which is closer to 1, which represents parity with N3. Since it's an optical shrink, it should also apply to SRAM and analog as well. Throw in a higher density SRAM bitcell, which I believe was in the works anyway, and you've clawed back almost all of the density that you'd otherwise lose going from N3 to N3E.

Being based on N3E, N3S should get the same power and performance gains while also using fewer EUV steps. That means lower complexity, better yields, and shorter cycle times, which would further reduce costs.

 

[A///]

Apple's urge to use n3e over the lackluster n3 isn't at all required at the moment given how efficient and powerful their devices are. while tsmc is addressing their issues that benefit of this current poor economy is helping apple not have to be ready and flush with n3e made hardware as everyone is recoiling at current pricing and scaling back their personal spend.

 

[Doug S]

Bigger numbers are better.

Ah yes I was looking at it backwards, thinking it was showing shrink not density.

 

[smalM]

Even the original N3 they are saying that they won't recognize sizable revenue until Q3, which more likely means that whatever is using it isn't coming out until next year at the earliest.

No.
Revenue is only recognized after the chip is sent to the customer, which is more than 3 month after wafer start.

 

[oak8292]

No.
Revenue is only recognized after the chip is sent to the customer, which is more than 3 month after wafer start.

I believe that TSMC is doing all of the packaging for Apple on both A and M processors which means that revenue recognition probably follows packaging. It seems like there is an inventory build at TSMC prior to revenue from Apple in fall.

 

[A///]

any decent leads on what will be presented @ wwdc or is it all kuo and the bloke from bi spewing their regular details?

 

[Ajay]

If someone here has a good link that explains Apple's M series SLC, I would appreciate it. My google-fu appears to suck. TIA!