Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[poke01]

Apple’s A17 Bionic Barely Beats The A16 Bionic In New Multi-Core Leak, Only Manages A 10 Percent Improvement In Single-Core Result

The A17 Pro is a 3nm SoC, but it fails to deliver a substantial single and multi-core performance lead over A16 Bionic, according to new leak

wccftech.com

Looks like tsmc n3 node is bad or arm isa has it a brick wall.. even apple said a17 has a wider decode than a16 🙄

I mean I could have said x86 hit a brickwall during Intels Skylake or AMDs Bulldozer days.

No ISA can hit a dead wall it's all about the designs

 

[A///]

Apple’s A17 Bionic Barely Beats The A16 Bionic In New Multi-Core Leak, Only Manages A 10 Percent Improvement In Single-Core Result

The A17 Pro is a 3nm SoC, but it fails to deliver a substantial single and multi-core performance lead over A16 Bionic, according to new leak

wccftech.com

Looks like tsmc n3 node is bad or arm isa has it a brick wall.. even apple said a17 has a wider decode than a16 🙄

Neither actually. TSMC n3 will continue to improve with time while N3E or N3P will go further. Apple license allows them to highly customize what they want. This is more like Apple beginning to hit a wall. For years apple spent time hitting low hanging fruit and amazing the masses. I predicted this issue back in the A10 days. There is only so much Apple can do without burning through capex. There is a reason they utilise accelerators for specific functions and tasks. x86 hit a wall at some point to and brushed past it. It's now Apple's turn to do it.

For the android market, they too are hitting a wall. It's all very interesting once you sit down and analyse the whole situation.

 

[A///]

I mean I could have said x86 hit a brickwall during Intels Skylake or AMDs Bulldozer days.

No ISA can hit a dead wall it's all about the designs

Neither of those were brick walls. Skylake's tenure was due to having to backport designs onto 14nm because intel were too aggressive with 10nm and they admitted to this a few years ago. Bulldozer was an interesting design on paper, it simply didn't pan out. Ryzen is how AMD got past their prior problem. Intel hasn't hit a wall yet, they did a shimmy shake to the side with their b.l design buying them such much needed time. Their tile approach may make it easier to stuff more cores and their move to gaafet and bspd will help. dlvr on mobile will help. ultimately intel will abandon b.l once they have something good in the tank. I would call Pentium 4 an actual wall. Intel went back to the drawing boards and came up with a revolutionary mildly recycled design. And they were kings of the castle for over a decade.

I'm one of the few people who think Intel's long hateful experience with the long 4-5 years of skylake was good training for them to pushing the limits within bounds. Raptor lake isn't perfect, nor is their refresh. I think Arrow Lake is where Intel is going to begin to shine. It'll give them enough time, hopefully, to come up with a better design. I don't necessarily se either AMD or Intel holding onto big.little in the far future.

 

[A///]

Don't forget Apple also lost a lot of top engineers to competitors in the last few years.

 

[Henry swagger]

Neither actually. TSMC n3 will continue to improve with time while N3E or N3P will go further. Apple license allows them to highly customize what they want. This is more like Apple beginning to hit a wall. For years apple spent time hitting low hanging fruit and amazing the masses. I predicted this issue back in the A10 days. There is only so much Apple can do without burning through capex. There is a reason they utilise accelerators for specific functions and tasks. x86 hit a wall at some point to and brushed past it. It's now Apple's turn to do it.

For the android market, they too are hitting a wall. It's all very interesting once you sit down and analyse the whole situation.

Yeah. Apple are still 2 gens infront of Android in cpu performance

 

[Doug S]

Apple’s A17 Bionic Barely Beats The A16 Bionic In New Multi-Core Leak, Only Manages A 10 Percent Improvement In Single-Core Result

The A17 Pro is a 3nm SoC, but it fails to deliver a substantial single and multi-core performance lead over A16 Bionic, according to new leak

wccftech.com

Looks like tsmc n3 node is bad or arm isa has it a brick wall.. even apple said a17 has a wider decode than a16 🙄

Before you say that's a brick wall let's see what Intel and AMD actually do, rather than all the fantastic claims of 20-30% generational IPC uplift being made for future CPUs by the enthusiasts in the Intel and AMD threads.

That said I was expecting a bit more of a boost from Apple since they've kind of stalled since the A14. Maybe the talent lost to Nuvia really hit them. I hope to at least see evidence there were some real changes to the design of A17's cores, since A15 and A16 had far fewer changes from A14 than Apple had been making in the past.




Use of the word fanboys is not allowed.



esquared
Anandtech Forum Director

 

[A///]

Yeah. Apple are still 2 gens infront of Android in cpu performance

Yep, ios while restricted compared to android is far more polished and cohesive, too.

 

[A///]

Before you say that's a brick wall let's see what Intel and AMD actually do, rather than all the fantastic claims of 20-30% generational IPC uplift being made for future CPUs by the x in the Intel and AMD threads.

I've never seen people who prefer Intel to say or make wild claims like that. AMD rumours and presentations have been more or less the same and AMD hasn't lied about their performance uplift with each generation of Zen. Their radeon division leaves a lot to be desired and fixed ofc.

Don't mix up the hype some parties like mlid or rgt push with the actual leakers near the presenation period.

 

[Glo.]

We're still at 24Gbit dies for LPDDR5 so no.

M3 will have wider bus. It will go up from 128 to 192, M3 Pro will go from 256 to 384 and M3 Max will go from 512 to 768 bit bus.

Thats how Apple will get higher capacities in each model.

 

[TESKATLIPOKA]

M3 will have wider bus. It will go up from 128 to 192, M3 Pro will go from 256 to 384 and M3 Max will go from 512 to 768 bit bus.

Thats how Apple will get higher capacities in each model.

Can a single LPDDR5 module use 128-bit wide bus by itself?
Because It looks like that for M2.

 

[Glo.]

Can a single LPDDR5 module use 128-bit wide bus by itself?
Because It looks like that for M2.

They are bog standard 64 bit chips with different packaging

 

[soresu]

Don't mix up the hype some parties like mlid or rgt push

To be fair RGT is a lot more level headed about it, they usually present rumours as rumors and do not pretend otherwise.

MLID on the other hand discusses them with the certainty of a company PR exec, which gives people the wrong impression.

 

[richardskrad]

https://twitter.com/x/status/1702148760535765134

A17 Pro Geekbench 6. Seems like there's 0% IPC gain. The 10% increase in ST performance is from overclocking. So Apple losing most of their best chip designers after the release on the M1 is true.

Wow... Apple has been on a slump since the A14, which came out in 2020. After the A17, Apple has now 4 back to back generations of very little progress both in terms of efficiency and CPU and GPU performance under their belt. Should we start ringing the alarm that Apple's chip division is in free fall?

 

[Glo.]

https://twitter.com/x/status/1702148760535765134

A17 Pro Geekbench 6. Seems like there's 0% IPC gain. The 10% increase in ST performance is from overclocking. So Apple losing most of their best chip designers after the release on the M1 is true.

Wow... Apple has been on a slump since the A14, which came out in 2020. After the A17, Apple has now 4 back to back generations of very little progress both in terms of efficiency and CPU and GPU performance under their belt. Should we start ringing the alarm that Apple's chip division is in free fall?

Considering that Apple delivers new SOC each year, making new CPU AND GPU design each year would be difficult for AMD and Intel and Nvidia. So why Apple would not be bound by the same problems to solve like other companies?

 

[Mopetar]

Apple delivers multiple SoCs on a yearly basis. Yes they share a lot of the same IP, but they're making their A-series for mobile devices, M-series for their Macs, S-series for their watches, along with various other chips for other products such as their AR goggles.

I wouldn't be surprised if they decided to leave the core mostly alone while focusing on all of the other things they've been doing. I wouldn't want to tell any company that they can rest on their laurels, but no one else seems like they're doing to much to catch up to Apple even while they're coasting.

 

[adroc_thurston]

M3 will have wider bus

No.

 

[Ajay]

They are bog standard 64 bit chips with different packaging

I thought LPDDR5 was 32b, unless there is a wider bus option in the spec.

 

[GC2:CS]

https://twitter.com/x/status/1702148760535765134

A17 Pro Geekbench 6. Seems like there's 0% IPC gain. The 10% increase in ST performance is from overclocking. So Apple losing most of their best chip designers after the release on the M1 is true.

Wow... Apple has been on a slump since the A14, which came out in 2020. After the A17, Apple has now 4 back to back generations of very little progress both in terms of efficiency and CPU and GPU performance under their belt. Should we start ringing the alarm that Apple's chip division is in free fall?

While the IPC gains are virtualy zero, the power consumption is supposedly going down with every generation since A13 which could take some 6W in single core. While the clock went up from 2,66 Ghz to 3,78Ghz.

I think this requires some serious engineering on the uarch even though the IPC has remained the same. Maybe this is the goal - higher Ghz at less power and Apple is activelly keeping the IPC the same to achieve that easilly.

We will see a 4Ghz iPhone next year for sure.

 

[adroc_thurston]

the power consumption is supposedly going down with every generation since A13 which could take some 6W in single core.

No it's been the same since ~A14.
A13 was an outlier (and a PPW regression).

Maybe this is the goal - higher Ghz at less power and Apple is activelly keeping the IPC the same to achieve that easilly.

the eternal Skylake is back babay

We will see a 4Ghz iPhone next year for sure.

Well. No.
N3p is a rounding error speed bump over N3b.

 

[trivik12]

3.8ghz for a mobile phone is nuts. I am waiting to see the battery tests on 15 pro max. Of course clock speed wont be this high for all the tasks.

I wonder how high this can go. with GAAFET will Apple go for 5ghz mobile SOC !!!

 

[ikjadoon]

So about a week until the A17 reveal. IPC-wise (let’s call it perf per clock in GB6), we should know roughly then when GB6 scores and clocks are inevitably leaked.

2+ years of iterating A14 perf, what now?

A. Less than 5% IPC uplift
B. 5% to 10% IPC uplift
C. 10% to 15% IPC uplift

This 2021 article comes to mind:

Apple CPU Gains Grind To A Halt And The Future Looks Dim As The Impact From The CPU Engineer Exodus To Nuvia And Rivos Starts To Bleed In

Apple's leading CPU team looks to be struggling as they have now delivered no CPU gains for the first generation ever. Apple likely had to delay their next core architecture due due to personnel overturn from the Nuvia exodus. Furthermore, with a new exodus surrounding Rivos, the future doesn't...

www.semianalysis.com

One thing we noted in the Arm thread is that Geekbench 6.1 & 6.2 scores are not comparable with Geekbench 6.0 scores.

OK, looking at the iPhone 15 Pro (A17 Pro) and using the top scores in the first two pages of results (to make sure it's GB6.1 / 6.2)

Apple A14: 2201 @ 2.99 GHz (736 pts / GHz - 100.0%)
Apple A15: 2387 @ 3.23 GHz (739 pts / GHz - 100.4%)
Apple A16: 2683 @ 3.46 GHz (775 pts / GHz - 105.3%)
Apple A17P: 2914 @ 3.77 GHz (773 pts / GHz - 105.0%)

So literally 0% IPC uplift / category A. So the 🏆 goes to @poke01. For now three generations, Apple has barely increased IPC by 5%. Efficiency: that would be interesting to test, but basically no one does serious testing on smartphone CPU power consumption. The A15, while basically no IPC, actually improved power consumption, even with notably higher clocks (5.5% lower avg power to 4.11W, 16.5% less energy, and 13-15% faster performance)

//

So even with improved branch prediction, wider decode, and wider execution: 0% IPC? On what programs / tests can you change those in a core and get zero IPC uplift? Unless clocks are wrong (which they rarely are), the CPU uArch seems like a clone of the past three uArches or those improvements are making up for some other deficiency not yet mentioned.

 

[trivik12]

In Isolation its still an impressive chip. Especially in Performance per watt. Let us see how MTL with on package RAM compares to it. I assume Zen 5 laptop also will have something similar to compare.
For a phone these chips crazy overkill. Most folks dont do anything beyond doing things that would work with 5 year old phone. OEM's slow down with s/w "improvements"/battery degradation makes older phone look worse after couple of years.

 

[Eug]

Most folks dont do anything beyond doing things that would work with 5 year old phone. OEM's slow down with s/w "improvements"/battery degradation makes older phone look worse after couple of years.

FWIW, we have a retired iPhone XR, which has the A12 SoC. It was released in 2018, which makes it 5 years old. It runs perfectly fine, but I can notice occasional lags now with it, running the latest version of iOS.

That said, the lag may have more to do with the 3 GB RAM than the SoC.

 

[Doug S]

I thought LPDDR5 was 32b, unless there is a wider bus option in the spec.

LPDDR is 16 bits. You use more controllers to go wider, though they are often grouped together since there is less need for 16 bit accesses these days. The standard does define a way of splitting access to get two 8 bit channels if byte addressability is necessary for certain devices (not sure how much that is used these days with multi gigabyte LPDDR5 but maybe with older revs that used less RAM...)

 

[Doug S]

FWIW, we have a retired iPhone XR, which has the A12 SoC. It was released in 2018, which makes it 5 years old. It runs perfectly fine, but I can notice occasional lags now with it, running the latest version of iOS.

That said, the lag may have more to do with the 3 GB RAM than the SoC.

iOS 17 supports phones with 2 GB so it shouldn't be visibly lagging. Maybe the .0.1 or .1 release will fix it? Or possibility it is related to the battery cells weakening and the SoC has to back down on power draw occasionally?