Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[Glo.]

Both Apple M2 and Radeon 780M have upto 100 GB/s of memory bandwidth (LPDDR5-6400, 128 bit)

Yet the Apple GPU is a bit more powerful,

View attachment 90523

I believe the reason is the tile architecture of Apple's GPU, which allows them to pack in more GPU performance to the same memory bandwidth.

I guess this applies to Qualcomm as well.

Apple GPU has 1280 ALUs for 128 bit bus, 780M has 768 ALUs for 96 GB/s on a 128 bit bus. X Elite has 1536 ALUs.

Only Strix Point will bring the ALU count of AMD iGPU to at least 1024 ALUs.

 

[FlameTail]

Apple GPU has 1280 ALUs for 128 bit bus, 780M has 768 ALUs for 96 GB/s on a 128 bit bus. X Elite has 1536 ALUs.

Only Strix Point will bring the ALU count of AMD iGPU to at least 1024 ALUs.

Talking about ALU count is next to useless. What about the clock speed? Other factors? It's like talking about TFLOPS. We all know how comparing TFLOPS is useless (unless it it's between GPUs of the same architecture).

 

[Glo.]

Looking at how meaningless performance updates we get with increases in clock speeds I'd say much more important is memory bandwidth for anything highly parallel(GPU workloads in general) than clock speeds.

And that - we can see with performance of the wide GPUs instead of fast GPUs, but narrow(in terms of ALU counts).

I know that this is oversimplification of things.

 

[FlameTail]

Can anyone guess what the size of the SLC is?

We do know that the CPU P-cluster L2 is 16 MB.

 

[Nothingness]

Can anyone guess what the size of the SLC is?

I let others do the guesswork for me: they claim 8MB.

 

[FlameTail]

I let others do the guesswork for me: they claim 8MB.

So it's been 8 MB for 3 generations since the M1 to M3.

 

[FlameTail]

Also, can I just say how cool the M3 Max looks with those 2 MASSIVE SLC slices + memory controllers, which are flanking the GPU.

Like a rocket with 2 boosters on the side. You get what I mean

 

[mikegg]

“The M2 family was really now about maintaining that leadership position by pushing, again, to the limits of technology. We don’t leave things on the table,” says Millet. “We don’t take a 20% bump and figure out how to spread it over three years…figure out how to eke out incremental gains. We take it all in one year; we just hit it really hard. That’s not what happens in the rest of the industry or historically.”

Apple execs on M2 chips, winning gamers and when to buy a Mac | TechCrunch

Apple's M series chips were incredibly well telegraphed when they arrived in late 2020. Apple had been designing its own silicon since the A4 appeared in

techcrunch.com

What do you think this Apple executive is implying in this quote?

 

[FlameTail]

M2 -> M3
155 mm² -> 146 mm²
N5P -> N3B

A16 -> A17
113 mm² -> 103 mm²
N4 -> N3B

The M3 die hasn't shrink as well as the A17 has. A17 has a 10 mm² reduction from A16, while M3 only has a 9 mm² reduction from M2, despite the latter having a wider node difference and bigger die size than the A17-A16.

Where did all the extra transistors go in the M3?

I think at this rate, the M4 will exceed 170 mm², since it will certainly use N3E/N3P, which brings no density improvement over N3B.

 

[Nothingness]

“The M2 family was really now about maintaining that leadership position by pushing, again, to the limits of technology. We don’t leave things on the table,” says Millet. “We don’t take a 20% bump and figure out how to spread it over three years…figure out how to eke out incremental gains. We take it all in one year; we just hit it really hard. That’s not what happens in the rest of the industry or historically.”

...

What do you think this Apple executive is implying in this quote?

I think he means every improvement to the micro arch or implementation that has been identified as worth the cost is going into the very next design.

Sometimes design teams find something interesting but push it to the next iteration because the current design has enough improvements. And also because they just don't have the time to do it properly. Apple has more resources in their CPU design teams than most (all?) other companies so they can afford being aggressive.

 

[GC2:CS]

Qualcomm claims the Snapdragon Elite X is 21% faster than M3

the article does not have a source though Who got the acces to the device then ? Dont be shy I know you are somewhere on this forum.

Qualcomm Claims Snapdragon X Elite 21% Faster Than Apple's M3 Chip

Chipmaker Qualcomm has claimed that its new Snapdragon X Elite PC processor is 21% faster than Apple's latest M3 chip in multi-core performance,...

www.macrumors.com

 

[FlameTail]

Qualcomm claims the Snapdragon Elite X is 21% faster than M3

the article does not have a source though

I believe Qualcomm actually gave an 'end of year update' to the press. Macrumours isn't the only one reporting this. Notebookcheck, Digital Trends, and Forbes did too.

Who got the acces to the device then ? Dont be shy I know you are somewhere on this forum.

Well, the lead architect who actually designed the Oryon CPU is literally in this forum.

 

[Doug S]

It isn't surprising that M3 gets beat in MT, since it is 4P+4E and Oryon is 12P.

 

[gdansk]

It is surprising, to me, that 12 Oryon can be included in a reasonably small die. Not much bigger than M2/M3.

 

[SpudLobby]

It is surprising, to me, that 12 Oryon can be included in a reasonably small die. Not much bigger than M2/M3.

This is the money shot really. It’s on a 170 mm^2 die on N4P and packs a great display engine (3x 4K), a hefty encode/decode engine, powerful GPU and NPU still.

And as importantly the cores look to be pretty efficient or performant (and efficient still) in ST on their own. So it’s not just like 16 Crestmonts or even AMD’s Zen 4c crammed in. Much better than that.

 

[SpudLobby]

But overall sure the M3 is still very impressive for a 4 + 4 part. It is also on N3B which doesn’t hurt here seeing as power looks decent and frequencies are gunned.

 

[FlameTail]

It isn't surprising that M3 gets beat in MT, since it is 4P+4E and Oryon is 12P.

Anyone with atleast 1 braincell shouldn't be surprised

 

[FlameTail]

This is the money shot really. It’s on a 170 mm^2 die on N4P and packs a great display engine (3x 4K), a hefty encode/decode engine, powerful GPU and NPU still.

And as importantly the cores look to be pretty efficient or performant (and efficient still) in ST on their own. So it’s not just like 16 Crestmonts or even AMD’s Zen 4c crammed in. Much better than that.

Indeed. It's the golden bullet. That the die size is surprisingly compact, which means production costs are leashed in.

 

[FlameTail]

Eventually Apple's M Max chips will also have to use chiplets.

In the generation that begins to use High-NA EUV.

High-NA EUV halves the reticle size to 429 mm².

M2 Max and M3 Max are well over 430 mm² I believe. So future Max chips cannot be monolithic.

 

[LightningZ71]

It's becoming fairly obvious that the whole industry of high performance chips will head that way. I do think that they will do it in stages by pushing off every bit of I/O that's not RAM controller onto a second chiplet first. I also think that they're going to find themselves in a situation where cache scaling is falling way too far behind, and their higher end chips will need a stacked L3/SLC.

 

[Doug S]

Eventually Apple's M Max chips will also have to use chiplets.

In the generation that begins to use High-NA EUV.

High-NA EUV halves the reticle size to 429 mm².

M2 Max and M3 Max are well over 430 mm² I believe. So future Max chips cannot be monolithic.

Well Apple is already using chiplets for Ultra. So maybe instead of two Max = one Ultra we have two Pro = one Max and four Pro = one Ultra.

 

[mikegg]

is going into the very next design.

But that's not what he said. He said "we take it all in one year". Why do you think you said "one year" instead of "next design"?

 

[mikegg]

Eventually Apple's M Max chips will also have to use chiplets.

In the generation that begins to use High-NA EUV.

High-NA EUV halves the reticle size to 429 mm².

M2 Max and M3 Max are well over 430 mm² I believe. So future Max chips cannot be monolithic.

It can be. Max chips are around ~430mm2 right now. All Apple has to do is make it slightly smaller. It seems like Apple has been designing the Max chip in anticipation of this limit all along.

 

[eek2121]

FYI, the NPUs are probably way slower than GPUs at ML acceleration.

Sure, for now. Just wait until the competition gets going.

 

[TESKATLIPOKA]

Sure, for now. Just wait until the competition gets going.

And then what? Half of the entire SoC will be NPU? How pointless.
I just don't understand all this hype about AI. Call me If It can really do something useful.