Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[FlameTail]

And then what? Half of the entire SoC will be NPU? How pointless.
I just don't understand all this hype about AI. Call me If It can really do something useful.

I think you guys are overestimating how much die area the NPU takes.

Idk about Meteor Lake and Phoenix, but on the Apple A17 Pro, the NPU has 35 TOPS and is a mere 5mm².


And M3 has half of that at 17 TOPS.

Similar story in Qualcomm chips:

 

[TESKATLIPOKA]

I think you guys are overestimating how much die area the NPU takes.

Idk about Meteor Lake and Phoenix, but on the Apple A17 Pro, the NPU has 35 TOPS and is a mere 5mm².

View attachment 90881
And M3 has half of that at 17 TOPS.
View attachment 90882
Similar story in Qualcomm chips:
View attachment 90883

I was not talking about current products.

 

[igor_kavinski]

Call me If It can really do something useful.

It can draw cat pics. What more do you want? You can has all the cat pics you could ever want.

 

[TESKATLIPOKA]

It can draw cat pics. What more do you want? You can has all the cat pics you could ever want.

Ok. To be honest AI pictures on web look pretty nice.

P.S. here is your cat

 

[Doug S]

It can be. Max chips are around ~430mm2 right now. All Apple has to do is make it slightly smaller. It seems like Apple has been designing the Max chip in anticipation of this limit all along.

Not really. The M1 Max was claimed to be around that size based on die photos Apple had supplied. Then someone actually looked at one, and noticed all that extra space at the bottom that turns out to be for connecting two Max dies together that was cut out of Apple's die photo. The actual size was around 500 mm^2.

That's not to say they couldn't release a more compact version by the time high NA comes around. The caches may not shrink much (though BSPD may help there) but logic will, even if not as much as it used to. So Apple could probably produce one in TSMC's A14 or A10 with more cores for everything than today that fits the smaller reticle. And while they may want to add more CPU/GPU/NPU cores they aren't going to need to increase the number of memory controllers, TB ports, displays supported and so forth. So to the extent that stuff can shrink they will claw back some area.

 

[FlameTail]

"The timeline for N2 involves risk production in 2025, leading to volume ramp in the second half of the year.

TSMC will offer a version of N2 with BSPDN later in the cycle - approximately six months later ."

- https://morethanmoore.substack.com/p/tsmc-oip-forum-fabs-n3n2bspn

Based on this timeline, I don't think Apple A19 will be using N2.

A19 is a 2025Q3 chip, and N2 is ramping in 2025H2. The timing does not align.

So,

2023 = A17 = N3B
2024 = A18 = N3E
2025 = A19 = N3P
2026 = A20 = N2 (+BSPDN?)
2027 = A21 = N2P (+BSPDN?)

 

[Glo.]

TSMC will offer a version of N2 with BSPDN later in the cycle - approximately six months later ."

Will be there also BDSM version?

 

[SiliconFly]

Will be there also BDSM version?

Only for mac fans

 

[SpudLobby]

Eventually Apple's M Max chips will also have to use chiplets.

In the generation that begins to use High-NA EUV.

High-NA EUV halves the reticle size to 429 mm².

M2 Max and M3 Max are well over 430 mm² I believe. So future Max chips cannot be monolithic.

A good question is: what kind of advanced low power chiplet tech is on the table? There are a lot of different ways to do this afaict. My hope is Apple, MediaTek, Nvidia, Qualcomm find ways to do chiplets without utterly screwing idle power and active power.

Idk there’s so many d*mn packaging technologies from AMD’s cheap BS to Intel’s EMIB and Foveros Omni stuff.

But looking at Lunar Lake Intel apparently thinks the 4 tile stuff was too far — and apparently Panther Lake is more similar to Lunar Lake than MTL/ARL.

I think a CPU and GPU tile, with SOC and IO function siphoned into one of those, and on some kind of very very low power interposer might have a lot of potential going forward for mobile APUs or desktop. It’s the only way we’ll see some beefy M Pro/Max type setup from Nvidia or Intel etc.

 

[mikegg]

Sure, for now. Just wait until the competition gets going.

I argued that we'll have giant NPUs with a CPU and GPU attached to it: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...us-with-a-cpu-and-gpu-attached-to-it.2611174/

Currently, SoCs are giant CPUs or giant GPUs with an NPU attached to it.

 

[mikegg]

Not really. The M1 Max was claimed to be around that size based on die photos Apple had supplied. Then someone actually looked at one, and noticed all that extra space at the bottom that turns out to be for connecting two Max dies together that was cut out of Apple's die photo. The actual size was around 500 mm^2.

That's not to say they couldn't release a more compact version by the time high NA comes around. The caches may not shrink much (though BSPD may help there) but logic will, even if not as much as it used to. So Apple could probably produce one in TSMC's A14 or A10 with more cores for everything than today that fits the smaller reticle. And while they may want to add more CPU/GPU/NPU cores they aren't going to need to increase the number of memory controllers, TB ports, displays supported and so forth. So to the extent that stuff can shrink they will claw back some area.

Interesting. I did not know the actual size was that big. Then separate dies seem to be the only logical choice.

 

[FlameTail]

A good question is: what kind of advanced low power chiplet tech is on the table? There are a lot of different ways to do this afaict. My hope is Apple, MediaTek, Nvidia, Qualcomm find ways to do chiplets without utterly screwing idle power and active power.

Idk there’s so many d*mn packaging technologies from AMD’s cheap BS to Intel’s EMIB and Foveros Omni stuff.

But looking at Lunar Lake Intel apparently thinks the 4 tile stuff was too far — and apparently Panther Lake is more similar to Lunar Lake than MTL/ARL.

I think a CPU and GPU tile, with SOC and IO function siphoned into one of those, and on some kind of very very low power interposer might have a lot of potential going forward for mobile APUs or desktop. It’s the only way we’ll see some beefy M Pro/Max type setup from Nvidia or Intel etc.

Yes.

**Tile A** : CPU, NPU, ISP, Security Processor, I/O, Display Engine

**Tile B** : GPU, Media Engine,

With RAM buses and SLC on both tiles.

This allows for good product segmentation too, as you can mix and match CPU and GPU tiles, to create several SoCs.

 

[FlameTail]

What's taking up all the unlabeled area in the M3?

One would assume the CPU, GPU, NPU would take up much of the die area in such an SoC. But looking at this die shot, there's a lot of unlabeled area. What's in all that?

I can think of the Media Engine, Secure Enclave and Image Signal Processor. What else?

 

[SteinFG]

I can think of the Media Engine, Secure Enclave and Image Signal Processor. What else?

Also NVMe phy and controller, Couple USB phy and controllers, Maybe Keyboard/Trackpad port (if it doesn't use USB), Ethernet phy and controller.

 

[FlameTail]

"The timeline for N2 involves risk production in 2025, leading to volume ramp in the second half of the year.

TSMC will offer a version of N2 with BSPDN later in the cycle - approximately six months later ."

- https://morethanmoore.substack.com/p/tsmc-oip-forum-fabs-n3n2bspn

Based on this timeline, I don't think Apple A19 will be using N2.

A19 is a 2025Q3 chip, and N2 is ramping in 2025H2. The timing does not align.

So,

2023 = A17 = N3B
2024 = A18 = N3E
2025 = A19 = N3P
2026 = A20 = N2 (+BSPDN?)
2027 = A21 = N2P (+BSPDN?)

Will BSPDN even be available on time for A20?

 

[GC2:CS]

It can draw cat pics. What more do you want? You can has all the cat pics you could ever want.

Can it do a 10/10 loaf ? If not then the real cat will always reign supreme over the AI cat.

Will be there also BDSM version?

Those abreviations are getting ridicoulous. Somebody was explaining to me how BSPDN is amazing and is going to change the semi landscape in a year. And I was like hmm… that sounds like some old backside power delivery stuff Lets call it dual flip for double the jam !

A good question is: what kind of advanced low power chiplet tech is on the table? There are a lot of different ways to do this afaict. My hope is Apple, MediaTek, Nvidia, Qualcomm find ways to do chiplets without utterly screwing idle power and active power.

Idk there’s so many d*mn packaging technologies from AMD’s cheap BS to Intel’s EMIB and Foveros Omni stuff.

But looking at Lunar Lake Intel apparently thinks the 4 tile stuff was too far — and apparently Panther Lake is more similar to Lunar Lake than MTL/ARL.

I think a CPU and GPU tile, with SOC and IO function siphoned into one of those, and on some kind of very very low power interposer might have a lot of potential going forward for mobile APUs or desktop. It’s the only way we’ll see some beefy M Pro/Max type setup from Nvidia or Intel etc.

Nah I am pretty sure you dont need EUV to pattern for the die to die interconects. That is some aluminium stuff. Would be an Apple way of cheating the reticle limit by a bit.

 

[FlameTail]

So the M3 Pro and Max ditched the 4 core CPU cluster and migrated to a 6 core CPU cluster.

4 cores/16 MB L2 -> 6 cores/24 MB L2

What are the pros/cons of this change?

For one, I guess single threaded performance would benefit as one core has access to 24 MB L2.

But then what is the effect on MT performance? The amount of L2 per core is the same in both the 4C/16 MB and 6C/24 MB clusters.

 

[Doug S]

But then what is the effect on MT performance? The amount of L2 per core is the same in both the 4C/16 MB and 6C/24 MB clusters.

It would hurt MT performance, because you have six cores snooping on that cache rather than four. For parallel tasks that don't talk to each other (i.e. Cinebench type stuff) it wouldn't make a difference, but where the cores are competing to access the same cache lines it would have a measurable impact.

 

[DrMrLordX]

Those abreviations are getting ridicoulous.

BSPDN is right up there with DLDO.

 

[igor_kavinski]

BSPDN is right up there with DLDO.

I wonder why they have to call it backside and not underside.

 

[FlameTail]

I wonder why they have to call it backside and not underside.

USPDN?

Nah mate. I am done with these names.

 

[soresu]

I wonder why they have to call it backside and not underside.

Probably it's related to how they architect image sensors with 'backside illumination' for greater sensitivity because the wiring has moved from the front side (top) of the sensor stack to the back side (bottom).

Honestly I'm surprised given how old BSI sensor tech is that it's took semiconductor logic this long to start using the same technique.

Perhaps the benefits weren't as clear prior to GAA/MBCFET/Nanosheet/RibbonFET.

 

[smalM]

I wonder why they have to call it backside and not underside.

Depending on how the die is bonded, the underside may be the frontside or the backside of the die.

So the M3 Pro and Max ditched the 4 core CPU cluster and migrated to a 6 core CPU cluster.

They all use the same uncore shared logic, M3 is just missing two cores.
I wouldn't be surprised if it is an 8 port cluster unit so they are more flexible in their chip design.

 

[FlameTail]

It would hurt MT performance, because you have six cores snooping on that cache rather than four. For parallel tasks that don't talk to each other (i.e. Cinebench type stuff) it wouldn't make a difference, but where the cores are competing to access the same cache lines it would have a measurable impact.

Then it case I think Apple should have stuck with 4 core clusters. Comparing M3 vs M3 Pro/Max, the ST performance difference is minimal, which shows that the extra cache isn't helping that much.

But more importantly it would have allowed them to this:

M3: 4P + 4E
M3 Pro : 8P + 4E
M3 Max : 12P + 4E

How neat is that!

 

[FlameTail]

Anyone here have a Macbook with M3 Pro or M3 Max?

On the CPU side, there is a performance cluster with 4 cores that reach a maximum of 4.056 GHz (or ~3.6 GHz when all cores are loaded) and an efficiency cluster with 4 cores that reach a

- https://www.notebookcheck.net/Apple...ormance-and-improved-efficiency.766789.0.html

I want to know if it's only the base M3 showing this behaviour, where under all-core load, the max speed is 3.6 GHz.