Yeah, that would seem more reasonable. We've seen P10 at 850MHz competing against a stock 950, though it's unknown what the GPU utilization was under vsync for both those cards. Hard to say whether it will scale the significant amount it would need to to move from competing with a 950 to competing with a stock 380, but it doesn't seem unlikely that the demo P10 was tuned down quite a bit to maximize the efficiency for demo purposes and there might be decent bit more power on tap.
I think raghu is completely out to lunch on it hitting 380 levels @ 50W though.
The demo Polaris 10 could be a cut off die (not full Polaris 10)
Remember the 1.25Ghz Fiji from that site
And 3GB for 2048bit HBM also sounds odd.
Unfortunatelly I can't.
There was one guy, called Cloudfiresomething. You should have seen how he was hyping the Maxwell on Notebookreview forum. That was good laugh.
Could be. There's no reason to think that since it would be counter-productive to their aims in that test, but maybe they had issues where they couldn't show a full die.
Too bad Ian never commented on how many GDDR5 modules the card used in the demo had, assuming they got to see the PCB. It would have been nice to know if it had four or eight GDDR5 modules.
That's because the Sandra results describe crazy and entirely wrong configurations. For instance, when I run the bench Sandra 2016 describes my config as 2X R200 series with 8GB DDR3 on a 512-bit bus.
I have already addressed that with my another post on the topic.
http://forums.anandtech.com/showpost.php?p=38033692&postcount=396
2048 Bit ,3 GB RAM.
With 2 GB stacks, you would have 2 cubes, both 1024 bit one would be 2 GB and second would 1 GB.
http://techreport.com/news/27676/samsung-starts-making-8gb-gddr5-memory-chips
With the availability of 8 Gbit GDDR5 chips almost a year back we can have 4 GB capacity with a 128 bit GDDR5 memory bus. The PS4 uses just 8 chips to achieve 8 GB capacity on a 256 bit GDDR5 memory bus. I would like to see 4GB as the default configuration on full Polaris 10.
Umm, that doesn't explain it at all. Why then do my 290s show a 512-bit DDR3 bus, official user CAS shows a 290X with 3GB DDR5, R9 Fury X (or Nano) shows 3GB DDR5 @ 2GHz on a 2048-bit bus, and R9 Fury shows 3GB of no type specified on a 500MHz 4096-bit bus.
If you look at the high cryptography list sorted by performance, none of those AMD results are valid configurations.
All I say is that it is completely possible to make 3 GB HBM2 GPU with 2 stacks of RAM.
As I said, it could be engineering sample only, and only for experimental purposes.
Not sure what capacity has to do with it, though I'd agree that 4GB is likely to be the default full chip config. It would be interesting to see because 4 chips would imply a 128-bit bus, while eight chips would almost certainly be a 256-bit bus.
http://www.anandtech.com/show/9886/amd-reveals-polaris-gpu-architecture
The Polaris chip demoed at CES was smaller than GK107 (118 sq mm) and Cape Verde(123 sq mm). I would guess its a 110 sq mm chip. Such a tiny chip means we are looking at a 128 bit GDDR5 memory bus. A 256 bit memory controller cannot be fit on such a small chip as it does not have the area for I/O pads for a 256 bit GDDR5 bus.
You forget some new posters claimed that Fury X will be 40% faster then Titan X and they diapered after Fury X release. Lack of hype control from AMD.
Que? Source for that rather dubious statement, please?
Edit: Not the statement that it won't have a 256-bit bus of course. Just the one that it's physically impossible to fit more than the couple hundred pads you need for a 128-bit GDDR5 bus.
Don't bother entertaining the possibility such a small chip like Polaris 10 to have a 256 bit bus, that goes against logic of designing efficient and cost effective chips for the LOW-END segment.
Regardless, it doesn't need it. Faster GDDR5 + 128 bit bus + next-gen bandwidth compression = more than enough for 380 class performance.
well fury X should be alot faster than TITANX.But AMD fuck up design with only 4x pipeline and 64rops.
On paper fury X should be like 20% faster than TITANX.
But in reality because same front end from hawaii with 4x pipelines its not much faster than 2800SP 390x despite it have 4100SP.
Can you point out a single GPU in the last 8 years since GDDR5 launched which had a 110-120 sq mm GPU with a 256 bit GDDR5 bus.
To give you an idea of GPU layout here are pics of Tahiti, Pitcairn and Cape Verde
http://www.anandtech.com/show/6210/amd-southern-islands-gpu-die-shots-released
btw the reason for these tiny GPUs (100-120 sq mm) to have 128 bit memory bus is also size and cost. Smaller memory bus translates to smaller boards with lesser number of PCB layers which makes them cheap to produce.
is it confirmed polaris 10 is GDDR5? because such a small chip with one or 2 stacks of HBM would be really good. Especially in laptops. No need for stacks on the PCB, traces on the PCB. Could be ridiculously tiny board for desktop.
Would be waste building it for gddr5
Raja held up an unsoldered GPU for the press to see, and no one mentioned that it was an HBM on interposer design.
The Polaris chip demoed at CES was smaller than GK107 (118 sq mm) and Cape Verde(123 sq mm). I would guess its a 110 sq mm chip. Such a tiny chip means we are looking at a 128 bit GDDR5 memory bus. A 256 bit memory controller cannot be fit on such a small chip as it does not have the area for I/O pads for a 256 bit GDDR5 bus.