ASML said:http://www.asml.com/asml/show.do?lang=EN&ctx=5869&rid=50869
(...)
"Our EUV program showed substantial progress in the quarter. All installed NXE:3300B systems have been upgraded to a wafer processing capability of more than 500 wafers per day. Two customers conducted endurance tests that demonstrated this capability of more than 500 wafers in a 24-hour period. We continue executing programs that should consistently deliver this level of performance, which our customers require by the end of the year. As planned, we recognized two EUV systems in revenue in the quarter; another system started exposing wafers in October and will be included in Q4 sales. We are working with a customer towards a mid-node insertion of EUV at the 10 nanometer logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment. In this scenario we expect to ship around six NXE:3350B systems starting mid-2015, on top of the three NXE:3300B systems that will be converted to NXE:3350B configuration," Wennink said.
Intel just stated they couldn't bet that EUV would be available in time for the 10 or 7nm node. If they bet on EUV and it wasn't available, they could be waiting many months or longer etc.
Does that late-2016 refer to 10nm availability or the "mid-node insertion" part?
Is production of 500 wafers in 24 hours adequate for high volume production? This sounds like an important milestone. Is it enough?
Is it certain to be Intel, or could it be TSMC?
Is it certain to be Intel, or could it be TSMC?
It wasn't explicitly said, however the timeline immediately disqualifies anyone but Intel as a candidate.The title is misleading. ASML's Peter Wennink didn't say that the customer is Intel.
It's TSMC and not Intel.
For instance here:
http://cens.com/cens/html/en/news/news_inner_47097.html
TSMC has publicly stated multiple times it's intentions to insert EUV as a
mid node simplifier for 10nm.
Not a well defined question because the easy answer here is "yes, of course, it just means they need to buy more tools to compensate for the lower throughput".
But I'd guesstimate that 500 wfrs/day is probably good enough to get it implemented in say one or two key mask levels where a single-pass on a low throughput EUV tool would supplant a quad-immersion printing step in the process flow. That might provide compelling enough economics to make the equation balance out in favor of EUV at that throughput.
It wasn't explicitly said, however the timeline immediately disqualifies anyone but Intel as a candidate.
Mid-node insertion means the node will already be in production and this would qualify as a post-production requal.
My interpretation of this wording is that Intel's POR (plan of record) is to put 10nm into HVM production in 1H 2016 with multi-patterning immersion litho with the intention of requaling the node in 2H 2016 using EUV tools to replace key critical litho steps.
It is a fairly low-risk way of transitioning to EUV without introducing any risk to production. Should the EUV transition effort fall on its face, they still have Plan A to fall back on.
In all, nothing but good news here really.
Not a well defined question because the easy answer here is "yes, of course, it just means they need to buy more tools to compensate for the lower throughput".
But I'd guesstimate that 500 wfrs/day is probably good enough to get it implemented in say one or two key mask levels where a single-pass on a low throughput EUV tool would supplant a quad-immersion printing step in the process flow. That might provide compelling enough economics to make the equation balance out in favor of EUV at that throughput.
As of late 2014, wafer processing capability was more than 500 wafers per day with 50% availability (500 WPD0.5) or 42 WPH1.0 (500 WPD0.5 / 24 h / 0.5), with a target of 1,500 WPD0.5 or 125 WPH1.0 in 2016
Is it certain to be Intel, or could it be TSMC?
Tu quoque.Wrong.... Just wild speculation as usual here.
It's TSMC and not Intel.
TSMC will not use EUV lithography for its first 10 nm products, according to Liu, but the company is working with ASML to develop tools for the process technology.
There is still some way to go to catch 10 nm. Were looking for an entry point after 10 nm.
As Intel made clear, using EUV is all about economic reasons.A good technical reason is that TSMC uses high density 2D interconnect
compared to Intel's much simpler 1D interconnect. The Flash NAND industry
already works with 1D interconnects equivalent to Intel's 10nm node
and is doing so without EUV.
There's no such thing as a real node (anymore). One shoud never compare nodes on the base of its number. I regularly see people making the huge mistake, even AnandTech, of saying for example that 22nm -> 14nm is a bigger scaling than usual (which BTW is true, but..), because (22/14)² = 2.5, or in AnandTech's case, saying that 28->20nm will at most increase density by [100 / (28/20)²]%.This is a real 16nm process with 16nm half pitch word lines
(32nm pitch versus Intel's 52nm pitch)
That's correct.But this 500 wafer/day number will likely become higher still, right?
From Wiki:
Tu quoque.
I can point you directly to TSMC's latest earnings release; they will start production of their first FinFETs, which, if you can recall, they had nothing but good words about with regards to its health and yield, in mid-2015 with the real volume coming in 2017, and they will likely not use EUV, so you can see where you come out if you add 2+ years to that for their 10nm production.
TSMC said:We will not use EUV for our first 10nm products, , however -- our EUV team is still continuously working on EUV, hopefully to insert a few layers after the 10 nanometer process start to qualify as a follow up process simplification
ASML's Peter Wennink said:We are working with a customer towards a mid-node insertion of EUV at the 10 nanometer logic node expected in late 2016
It's Samsung.What do other people think?