The ISA bus is slower than the PCI bus. So, when the PCI bus wants to write to the ISA bus, it has to wait until the ISA bus is ready. Because the ISA bus is many, many times slower than the PCI bus, the PCI bus is normally stalled for a long time whenever a PCI cycle to the ISA bus is initiated. This prevents other devices from accessing the PCI bus and can cause problems for time-critical applications that need constant access to the PCI bus.
To prevent the PCI bus from stalling every time it tries to write to the ISA bus, many chipsets now come with an embedded 32-bit posted write buffer. This buffer is designed to store PCI-to-ISA writes and thus allows delayed transaction cycles to be generated. When enabled, the PCI bus immediately writes up to two 16-bit or four 8-bit data to the write buffer. The PCI bus can then be freed to perform other transactions. The buffer contents are independently written to the ISA bus when it's ready.
Now, the data in the write buffer won't reach the ISA bus any faster than usual. This is because they will only be written to the ISA bus when the next available ISA cycle starts. But the difference here is that the entire operation can now occur without tying up the PCI bus.
This BIOS feature controls the operation of that embedded 32-bit posted write buffer. If enabled, up to four bytes of PCI-to-ISA writes are buffered and the PCI bus is released after writing to the buffer. If Delayed Transaction is disabled, the PCI bus will bypass the write buffer and write directly to the ISA bus.
It's highly recommended that you enable this feature for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using an ISA card that is not PCI 2.1 compliant. Note that Delayed Transaction is only important if you are actually using ISA devices. It is of no consequence at all if you are not using any ISA devices or if your motherboard doesn't even come with ISA slots!