On PLX 'bridge' and shared PCIe:
The PLX chips on x870X2 do not split lanes i.e. 16x switched ~= 8x:8x. It is wrong to use 8x:8x performance of 4850 CF to predict performance of 4870X2
IIRC the 3870X2 has a 48 lane 3 port v1.1 PEX8547 switch (not a bridge) and thus each GPU gets full 16x access when it is granted and not 8x. The advantage of this is that since the PCIe connection to the north bridge carries bursty traffic (actual traffic pattern depends on the game), the impact of latency is reduced and bandwidth preserved, as opposed to the bandwidth bottlenecking that would occur with a fixed 8x:8x split.
In the 4870X2, the new switch (possibly PEX8648) will support v2.0 which will double the available data rate (though with slight latency increase).
Also its is rumored that inter GPU traffic will improve. Not sure if inter GPU traffic went through the NB (and memory) in the 3870X2 since the switch functionally could route traffic between the GPUs. So I expect, at the least, that inter GPU traffic is switched at the PEX chip, and if possible they might have a common/duplicate memory area.
So there is no basis yet to state that the 4870X2 will be bottlenecked by the 'bridge' unless you can provide stats that show that the traffic pattern on the bus is sustained at >50% for a 4870 (single or CF),and even then show that ( 2x individual data - common data) exceeds 100% of 16x in CF