Bare-die testing: A delidded 3770k, an H100, and 9 different TIMs

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sxr7171

Diamond Member
Jun 21, 2002
5,079
40
91
It should take A LOT of pressure to crack the die if the pressure is evenly distributed.

I see. So with this method we are applying quite a bit more than possible with springs but still pretty safe for the die?
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
I see. So with this method we are applying quite a bit more than possible with springs but still pretty safe for the die?

The pins in the socket basically act like one big cushioning spring-mattress as you increase the pressure on the CPU die. Until it bottoms out of course, then you could have some problems.

I think it is telling though that there haven't been an outcry of enthusiasts cracking their delidded CPUs. Plenty of people report killing their chips during delidding if they cut through the PCB in the wrong area by accident, but nothing about cracking the silicon during the bare-die mounting or relidding with the IHS in which case the IHS rests on the bare-die all the same.
 

24HZ

Member
May 25, 2013
52
0
0
I see. So with this method we are applying quite a bit more than possible with springs but still pretty safe for the die?

I don't know what the distribution of popular methods are but IDC wrote a good guide on springless mounting in this thread.

Im personally using H110 stock mount which uses springs in conjunction with 3mm worth of nylon washers to offset the loss of the IHS (~2.5mm). So technically I have 0.5mm of additional pressure on the die beyond the factory spec. However, since the factory spec was for a shitty concave block on the IHS, I don't know what the 0.5mm of pressure really means given all the variables I've changed.



Count me as a fan of methods using less parts and proper coil springs which gives you a bigger margin of error.

Edit: My 4770K is pretty bum. I didn't really get much OC headroom with the delid and I'm topped out at 4.5. I'm just going to run this as long as I can before new bins show up and if they OC better.
 
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crashtech

Lifer
Jan 4, 2013
10,554
2,138
146
Would it be fair to say that the average OC ceiling has come down slightly twice in a row now? Seems like 5.2 on SB was often attainable, which makes the average ultimate OC performance delta between SB and HSW pretty small.
 

sxr7171

Diamond Member
Jun 21, 2002
5,079
40
91
The pins in the socket basically act like one big cushioning spring-mattress as you increase the pressure on the CPU die. Until it bottoms out of course, then you could have some problems.

I think it is telling though that there haven't been an outcry of enthusiasts cracking their delidded CPUs. Plenty of people report killing their chips during delidding if they cut through the PCB in the wrong area by accident, but nothing about cracking the silicon during the bare-die mounting or relidding with the IHS in which case the IHS rests on the bare-die all the same.

I see. Thanks. So it's consistent across mounts and remounts.
 
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sxr7171

Diamond Member
Jun 21, 2002
5,079
40
91
Not liking the Haswell results, I have 4.8GHz on my 3570K no delid and a H80. I think I got lucky with my CPU. Seems like a delid improves temps which is great but no extra headroom.

I'd like to see what extreme methods could yield. Phase change, liquid N2 etc. Probably not too great.
 

bononos

Diamond Member
Aug 21, 2011
3,894
162
106
Would it be fair to say that the average OC ceiling has come down slightly twice in a row now? Seems like 5.2 on SB was often attainable, which makes the average ultimate OC performance delta between SB and HSW pretty small.
5.2? On what N2? Its sounds super high even for SB.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
Would it be fair to say that the average OC ceiling has come down slightly twice in a row now? Seems like 5.2 on SB was often attainable, which makes the average ultimate OC performance delta between SB and HSW pretty small.

I don't know about 5.2, but 5.0 seemed to be within reach for most enthusiasts who were willing to lap their 2600k (or 2700k) and combine it with some high-end air or water (lapped as well).

3770k definitely saw the distribution shift down a good 200 MHz, and it does appear from early reports that the 4770k brings a distribution that shifts down another 200MHz more.

Could be that 32nm was just way over-designed and Intel left a lot of untapped potential on the table by releasing such low-clocked SKUs. Could be that 22nm is right on target and it (the process node) was better managed to maximize having lower power numbers while delivering the targeted clockspeeds (so it intentionally left less OC headroom on the table, unlike 32nm).

Regardless how or why, it kinda makes it all a rather smoothed over snoozefest where the enthusiast has now had their choice of three successive chips which more or less deliver roughly the same performance and power consumption when fully maxed out in terms of high-end clockspeeds.

Hopefully 14nm brings something new to the table. 5.5GHz on air would be a welcome surprise, but non-socketed chips would not be great. (who can delid or lap that?)
 

Lepton87

Platinum Member
Jul 28, 2009
2,544
9
81
I don't know about 5.2, but 5.0 seemed to be within reach for most enthusiasts who were willing to lap their 2600k (or 2700k) and combine it with some high-end air or water (lapped as well).
If you are ballathefearedD) 5.5GHz is easy on SB on AIR and 4.8GHz is also easy on HW also on AIR

On a more serious note:

5.1GHz was not uncommon(like 5% of chips?), 5.2GHz was rare but doable on air.
 

crashtech

Lifer
Jan 4, 2013
10,554
2,138
146
I don't know about 5.2, but 5.0 seemed to be within reach for most enthusiasts who were willing to lap their 2600k (or 2700k) and combine it with some high-end air or water (lapped as well).

3770k definitely saw the distribution shift down a good 200 MHz, and it does appear from early reports that the 4770k brings a distribution that shifts down another 200MHz more.

Could be that 32nm was just way over-designed and Intel left a lot of untapped potential on the table by releasing such low-clocked SKUs. Could be that 22nm is right on target and it (the process node) was better managed to maximize having lower power numbers while delivering the targeted clockspeeds (so it intentionally left less OC headroom on the table, unlike 32nm).

Regardless how or why, it kinda makes it all a rather smoothed over snoozefest where the enthusiast has now had their choice of three successive chips which more or less deliver roughly the same performance and power consumption when fully maxed out in terms of high-end clockspeeds.

Hopefully 14nm brings something new to the table. 5.5GHz on air would be a welcome surprise, but non-socketed chips would not be great. (who can delid or lap that?)
Thanks for your assessment. 200MHz lower per refresh sounds more realistic than the guesstimates I've been throwing around.
 

njdevilsfan87

Platinum Member
Apr 19, 2007
2,331
251
126
I think this architecture is done. Forget 5.5ghz. We need to start low again like C2D ,where the clocks drop back down to 2.0-2.4ghz, but have a huge 60% or greater IPC improvement. Then we can once again make our way back up to 5ghz from there.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
I think this architecture is done. Forget 5.5ghz. We need to start low again like C2D ,where the clocks drop back down to 2.0-2.4ghz, but have a huge 60% or greater IPC improvement. Then we can once again make our way back up to 5ghz from there.

I know it isn't popular to talk about it, but that is basically what an Itanium-like microarchitecture would do. Double or quadruple the width, drop the clockspeeds so power stays reasonable, and get the compilers to do more work for you.
 

moonbogg

Lifer
Jan 8, 2011
10,637
3,095
136
I think this architecture is done. Forget 5.5ghz. We need to start low again like C2D ,where the clocks drop back down to 2.0-2.4ghz, but have a huge 60% or greater IPC improvement. Then we can once again make our way back up to 5ghz from there.

I'll dream with ya.
 

njdevilsfan87

Platinum Member
Apr 19, 2007
2,331
251
126
How do you get the adhesive off the PCB? I've been practicing delidding with some old Opterons using the hammer and vice technique. Delidding those has been pretty simple, but the adhesive on the PCB... I don't want to use a razor blade on the PCB and risk scratching it. Is there something that will dissolve it and not anything else, like alcohol or acetone?
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
How do you get the adhesive off the PCB? I've been practicing delidding with some old Opterons using the hammer and vice technique. Delidding those has been pretty simple, but the adhesive on the PCB... I don't want to use a razor blade on the PCB and risk scratching it. Is there something that will dissolve it and not anything else, like alcohol or acetone?

Use IPA soaked cotton-balls and vigorous scrubbing, or an IPA soaked dremel brush.

Checkout post #3 in the following thread:
http://forums.anandtech.com/showthread.php?t=2261855
 

sxr7171

Diamond Member
Jun 21, 2002
5,079
40
91
I know it isn't popular to talk about it, but that is basically what an Itanium-like microarchitecture would do. Double or quadruple the width, drop the clockspeeds so power stays reasonable, and get the compilers to do more work for you.

When do you think they'll roll that in. It can't come soon enough IMHO.
 

WhoBeDaPlaya

Diamond Member
Sep 15, 2000
7,414
401
126
If you are ballathefearedD) 5.5GHz is easy on SB on AIR and 4.8GHz is also easy on HW also on AIR
Don't forget his 470s @ 1.21JigaHertz
On a more serious note, his results were with a 4670K IINM. Turning off HT on our 4770Ks would give us a bit more thermal headroom.
 

24HZ

Member
May 25, 2013
52
0
0
How do you get the adhesive off the PCB? I've been practicing delidding with some old Opterons using the hammer and vice technique. Delidding those has been pretty simple, but the adhesive on the PCB... I don't want to use a razor blade on the PCB and risk scratching it. Is there something that will dissolve it and not anything else, like alcohol or acetone?

Razor is fine, just be careful. I got 99% of the adhesive off with a razor at a very very shallow angle with moderate down pressure. Didn't catch on the PCB at all. Smooth as silk. The rest I got rid of with IPA and swabs but you really don't need to get it 100% clean unless you feel like expending a lot of energy and time.

If you plan on putting the IHS back then you need to clean off the adhesive on the IHS side too. Again, a razor is fine followed with IPA. The razor is much more efficient than IPA so the more you take off with the razor the less grunt work you'll have to do with the IPA.
 

24HZ

Member
May 25, 2013
52
0
0
As promised:



You would think it would be easier to put the offset washers under the springs but in the case of the current gen Corsair waterblocks, the spring post is oddly shaped and not very easy to find washers that would fit.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
As promised:



You would think it would be easier to put the offset washers under the springs but in the case of the current gen Corsair waterblocks, the spring post is oddly shaped and not very easy to find washers that would fit.

I don't understand why they added stand-off washers to space out the distance between the backplate and the back of the motherboard

The backplate is already designed to have the proper clearance from the back of the mobo.

When I used my H100 backplate I just threaded screws up through it from the backside, the threads are standard (I forget what they are but I just took it to Home Depot and used their thread kit to measure it quick and free) and the screws cost me all of maybe 50 cents.
 

crashtech

Lifer
Jan 4, 2013
10,554
2,138
146
His method allows the slack to be taken up while using all the stock hardware, but makes the backplate non-functional.

One win, one loss. As long as the mobo does not flex excessively with his method, it's an easy and clean looking way to achieve the goal.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
His method allows the slack to be taken up while using all the stock hardware, but makes the backplate non-functional.

One win, one loss. As long as the mobo does not flex excessively with his method, it's an easy and clean looking way to achieve the goal.

I think I am confused (no big surprise there ), but how does he reuse all the stock hardware (except the backplate) when it is the stock standoff pins (the height) that are the problem in the first place?

All I replaced were the stock standoff pins. I'm quite baffled to think how one would be able to salvage using the same standoff pins but not be able to use the stock backplate

What am I missing here?
 
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