If those two are saying this then surely anybody can understand that this means the AnTuTu results are nowhere near reality. No crushing of ARM is going to be happening.
BTW, Francois Piednoel agreed with David Kanter on Twitter, that the AnTuTu benchmark is not so well suited and can be cheated. A mobile SPEC suite would be better.
If those two are saying this then surely anybody can understand that this means the AnTuTu results are nowhere near reality. No crushing of ARM is going to be happening.
Sadly we'll have to wait for actual useful benchmarks and power consumption numbers. But I can easily tell you how it can happen courtesy of Anand's recent investigation into the i5 vs i7 Haswell MBA, specifically the observed voltages on page 3. (Well, that combined with the little tidbit in the most recent Anandtech Podcast 21 when they were talking about Snapdragon 800 and how these high performance ARM SoCs are running at anywhere from 1.25V to 1.3V under load.) Because an ARM SoC running its cores at 1.3V in order to hit say 2.3 GHz versus Haswell running at 0.842V to hit the same speed... We already know that Haswell idle power consumption is roughly equivalent to current ARM SoCs. Then the basic equation for dynamic power consumption is (activity factor)*(capacitance)*(frequency)*(voltage squared) - the difference in voltage (1.3^2/0.842^2) basically means that Haswell (activity factor)*(capacitance) would have to be 2.38x that of the ARM SoC or greater in order for it to be less energy efficient. Do you really think ARM has some magical properties to its architecture that allow it to be that much better than what Intel can come up with? (And yes, the differences in operating voltage we're seeing here are quite simply obscene - I'll freely admit that I was quite surprised to see operating at voltages that low for Haswell.)
Woah woah woah. You cannot simply compare power consumption across completely different chips with completely different capacitance figures like that. That is absolutely and completely wrong. Based on the absolutely miniscule size of an ARM die compared to a Haswell die, there is a LOT less capacitance in the ARM die. Ergo the Haswell would absolutely need to use a lot less voltage to come remotely close to the figure of the ARM die. You're also saying that "Haswell only needs x volts and ARM needs x volts", while voltage requirements are absolutely a factor of binning and different quality processors require different voltages to hit target speeds.
I do think ARM has a magical property which allows it to consume much less power than Intel - it's called no giant x86 overhead. The simplicity of the ARM instruction set and lack of any decoding saves them SO much die space compared to Haswell, which has support for all kinds of legacy instructions and needs a chunk of silicon which is probably close to the entire size of an ARM core just to do instruction decode (including the micro op cache and such).
I think you're forgetting we are dealing with one chip that is tiny, and another that is a giant in comparison.
a bit off-topic and I get that you are comparing it to haswell but jaguar cores have the x86 overhead while only being slightly larger than a15, with similar performance and power levels...
Sorry I should have specified Haswell rather than x86. The use of u-ops cache and huge instruction sets are what makes the power overhead larger, rather than x86 by itself. It's the fact that it is LARGE x86, yes.
a bit off-topic and I get that you are comparing it to haswell but jaguar cores have the x86 overhead while only being slightly larger than a15, with similar performance and power levels...
But Jaguar has support for all the way up to AVX- I doubt AVX2 will make that much difference to die size. uOp cache, perhaps.
AMD's Jaguar single thread performance at 1ghz in Cinebench 11.5 is 0.26 pts compared to Atom/CloverTrail+ that scores at 1ghz scores 0.10 points and I am partially sure that ARM CPU's have similar IPC to CloverTrail+ as for Bay Trail...
Intel stated that Bay Trail is 50-60% faster thus at 1ghz should score 0.15 or 0.16, so its behind Jaguar in terms of IPC wise, the only thing I can agree that Bay Trail will have 1/2 of power consumption as CloverTrail+.
I read that refresh/successor to "Temash/Kabini" codenamed "Beema" will be out in Q2/Q3 2014 with Jaguar+ cores and will be produced in TSMC's 20nm fabs. So "Beema" could be an Bay Trail "killer", I am not aware if Bay Trail will have a 14nm successor by end of 2014 since there are no information's about it.
There aren't much info about "Beema", but I would not be shocked if "Beema" manages to get healthy 10 to 15% better performance clock to clock compared to "Temash/Kabini" and it will implement GCN 2.0/2.5 since its an 20nm chip.
AMD could decide to hold "Beema" on 28nm, depending on the situation. But since Apple decided to stay on 28nm for another year then chances of "Beema" being 28nm rather than 20nm are pretty slim. More available wafers/capacity for AMD/others.
Intel needs to improve its IGP performance and efficiency otherwise it could get swallowed and spit couple of times by ARM and AMD, also Intel should not restrain the potential of their Atom chips just because they don't want Atom's to eat into their high margin Y and ULV's.
Bay Trail will finds its own place, Jaguar is not really in the same league but "Beema" will be except it all depends on AMD's decisions where to focus and I really think Intel should question its self in a way since Bay Trail could have been a much better product.
Jaguar is 3.5mm2 sans l2. A7 is 0.5mm2 a15 what 1.6mm2? Looks like different products to me from size alone.
Atom is stripped of eg. the fat fpu and avx jaguar have. Excactly to enable higher freq without power going through the roof. Comparing performance at same freq makes no sense. Atom is targeted at phones. Jaguar stands zerro chance here, 20nm or not. Its to beefed up and the process is not performing anything like 22nm finfet. That goes for 20nm to.
Diffrent products. Atoms goes for the big market.
And I explained why that conclusion is flawed. Though technically I was slightly mistaken as there's no evidence of turbo being enabled for the Baytrail SKUs listed in that chart. It's still basically the same effect though - the TDP for each of those SKUs is almost certainly based upon running indefinitely at full frequency. The TDP values for the desktop and mobile variants are about as useful as ever (Intel has a habit of using the same TDP for a group of products so that the OEM will have to design for the top SKU). The embedded variants don't suffer from that problem, but as usual they have more of a buffer than necessary due to their intended market.He said why, the prevalence of lower clocked yet with a hefty TDP jump SKUs. This suggests that the truly low power dies are a small subset or that they are making Bay Trail on more than just their ultra-low power 22nm process they've been talking about in their push for mobile.
I'm not certain why I feel compelled to explain this, but hopefully some others who read the thread will find it useful. Dynamic power consumption is one of those basic formulas that applies to all semiconductors. Die size is irrelevant thanks to the activity factor - it only plays a direct part when it comes to leakage. Basically, assuming that voltage and frequency were equal you can have a massive die with a 1 mF capacitance (just making numbers up) that's doing nothing except adding two numbers together and hence have an activity factor of .000001 and it would consume the exact same dynamic power consumption as a simple adder with a 1nF capacitance and activity factor of 1.Woah woah woah. You cannot simply compare power consumption across completely different chips with completely different capacitance figures like that. That is absolutely and completely wrong. Based on the absolutely miniscule size of an ARM die compared to a Haswell die, there is a LOT less capacitance in the ARM die. Ergo the Haswell would absolutely need to use a lot less voltage to come remotely close to the figure of the ARM die. You're also saying that "Haswell only needs x volts and ARM needs x volts", while voltage requirements are absolutely a factor of binning and different quality processors require different voltages to hit target speeds.
I do think ARM has a magical property which allows it to consume much less power than Intel - it's called no giant x86 overhead. The simplicity of the ARM instruction set and lack of any decoding saves them SO much die space compared to Haswell, which has support for all kinds of legacy instructions and needs a chunk of silicon which is probably close to the entire size of an ARM core just to do instruction decode (including the micro op cache and such).
I think you're forgetting we are dealing with one chip that is tiny, and another that is a giant in comparison.
You don't look at various factors Krumme, this was just my opinion.
Jaguar is not aimed at the same market as Atom or ARM chips, I only just gave a rough image between CloverTrail/BayTrail/ARM compared to AMD's Jaguar.
Are you mad or something, sir
What should i be mad about?
Looks like all good products but different to me. The choice and competition have never been better for the 25 years this have been my hobby. That leads to better future products. When there is no compettion the companies look at it like a cach cow.
I'm not certain why I feel compelled to explain this, but hopefully some others who read the thread will find it useful. Dynamic power consumption is one of those basic formulas that applies to all semiconductors. Die size is irrelevant thanks to the activity factor - it only plays a direct part when it comes to leakage. Basically, assuming that voltage and frequency were equal you can have a massive die with a 1 mF capacitance (just making numbers up) that's doing nothing except adding two numbers together and hence have an activity factor of .000001 and it would consume the exact same dynamic power consumption as a simple adder with a 1nF capacitance and activity factor of 1.
The same concept applies in this case - Haswell may have a lot of extra x86 baggage, execution units, and be just plain massive by comparison. But that only hurts it in terms of leakage power. When it comes to dynamic power only a fraction of the logic is actually toggling and expending energy... and it would be simply astounding if Intel needed to use even 25% more transistors*clocks to do the same work as an ARM design does. (That is to say that Intel may use more transistors, but it also would finish the work in fewer clocks which is all we're concerned about when talking dynamic power.)
Also, the "x86 overhead" is nowhere near as much as a penalty as some would like to make it out as being. Yes, it does add a small amount of die space to the actual CPU core, but it's really not much. Especially since what you're really concerned about is the delta between the x86 decode logic and what ARM processors have. Yes, just because the ARM ISA is simpler doesn't mean it doesn't have a considerable amount of logic here... there's a reason why A15 has 5 stages for fetch and 7 for decode, rename, and dispatch (for comparison Silvermont has 3 stages for fetch and 7 for decode, rename, and dispatch.)
Oh, and with respect to the continued claims that Intel is only able to obtain these extremely low operation voltages on a cherry-picked few dies that bin extremely well... Eh, unfortunately there's no publicly available information to dispel amusing notion. But if Intel can meet demand and continue to show strong margins then why precisely does it matter? Unless you wish to claim that the non-Intel-supplied systems that Anandtech reviewed are somehow using cherry-picked Haswell silicon.
Look at the newest thread, Bay Trail specs leaked. I think AMD could actually compete after I looked at TDP's and I saw like, kinda sad about Intel but happy for AMD.
Not convinced:
Pentium N3510 QC 2.00 GHz 4.5W (SDP)/7.5W(TDP) BayTrail-M
A6-1450 QC 1.0-1.4 GHz 8W TDP
Please compare Atom E3823 to A6-1450 Temash and all Bay Trail's need an I/O chip that adds another 0.5-1.0 watt TDP/power consumption compared to Temash/Kabini that are full true SoC so this means that the Temash/Kabini chip its self is an I/O.
From available information and Intel claims, top of the line Bay Trail's GPU will be comparable to A4-1200/1250.
Please compare Atom E3823 to A6-1450 Temash and all Bay Trail's need an I/O chip that adds another 0.5-1.0 watt TDP/power consumption compared to Temash/Kabini that are full true SoC so this means that the Temash/Kabini chip its self is an I/O.
From available information and Intel claims, top of the line Bay Trail's GPU will be comparable to A4-1200/1250.
@ShintaiDK @blackened23
I was wrong, its not the I/O but chip involving controlling power, I think its called FCH chip or something. It controls eletricity, power consumption, etc...
There's no source for Snapdragon 800 currently. My original cited reference (Anandtech Podcast 21, while they were talking about Snapdragon 800) stated voltages in the 1.25 to 1.3 range for the Samsung Galaxy S4 I believe it was? All in a discussion of the fact that the ARM SoC vendors are running way outside of the ideal points in the voltage/frequency curve in order to deliver higher performance. My impression for the methodology is that it's also a software reported figure, but I see no reason to doubt it.The Haswell front-end and tendency for speed>power (compared to ARM) does mean it uses more power. Think about it like ripple carry adders vs carry look ahead - the ripple is smaller and uses less power, but it's much slower. Those are the optimizations something like ARM may use. Haswell/performance x86 goes with the CLA - it's faster, MUCH faster, but it uses a lot more die space and a lot more logic and power. I would say that's how Haswell's front end adds power use - it's fast, but it needs lots and lots of logic in order to have fast branch prediction and instruction decode. ARM avoids the majority of the decoding, and something like Jaguar uses less instruction sets and doesn't care quite so much about prediction, instead saving power. Haswell could absolutely use a significant amount more die area to execute the same task as ARM - because it gets the task done much faster.
All I'm saying about the voltage is that the figures seem kind of hand-wavey. Do you have the source for the Snapdragon numbers? I just want to see the methedology - measuring the voltage with hardware for snapdragon would not be comparable to just reading CPUZ with Haswell.
There's no source for Snapdragon 800 currently. My original cited reference (Anandtech Podcast 21, while they were talking about Snapdragon 800) stated voltages in the 1.25 to 1.3 range for the Samsung Galaxy S4 I believe it was? All in a discussion of the fact that the ARM SoC vendors are running way outside of the ideal points in the voltage/frequency curve in order to deliver higher performance. My impression for the methodology is that it's also a software reported figure, but I see no reason to doubt it.
As for your example... Last I checked ripple carry are similar in area to carry look ahead, they just roughly trade off 50% lower power consumption for 50% increased delay. But that's what I mean, there are lots of trade-offs that ARM can make to reduce power, but having 2.38x less logic activity for the same workload isn't all that feasible. And if Intel really started optimizing Haswell for power efficiency then it's even less likely for there to be that kind of delta. Again, just because die area is huge by comparison doesn't mean that active logic is equally disproportionate between the two designs.
Do you have the source for the Snapdragon numbers?