He said why, the prevalence of lower clocked yet with a hefty TDP jump SKUs. This suggests that the truly low power dies are a small subset or that they are making Bay Trail on more than just their ultra-low power 22nm process they've been talking about in their push for mobile.
And I explained why that conclusion is flawed. Though technically I was slightly mistaken as there's no evidence of turbo being enabled for the Baytrail SKUs listed in that chart. It's still basically the same effect though - the TDP for each of those SKUs is almost certainly based upon running indefinitely at full frequency. The TDP values for the desktop and mobile variants are about as useful as ever (Intel has a habit of using the same TDP for a group of products so that the OEM will have to design for the top SKU). The embedded variants don't suffer from that problem, but as usual they have more of a buffer than necessary due to their intended market.
Woah woah woah. You cannot simply compare power consumption across completely different chips with completely different capacitance figures like that. That is absolutely and completely wrong. Based on the absolutely miniscule size of an ARM die compared to a Haswell die, there is a LOT less capacitance in the ARM die. Ergo the Haswell would absolutely need to use a lot less voltage to come remotely close to the figure of the ARM die. You're also saying that "Haswell only needs x volts and ARM needs x volts", while voltage requirements are absolutely a factor of binning and different quality processors require different voltages to hit target speeds.
I do think ARM has a magical property which allows it to consume much less power than Intel - it's called no giant x86 overhead. The simplicity of the ARM instruction set and lack of any decoding saves them SO much die space compared to Haswell, which has support for all kinds of legacy instructions and needs a chunk of silicon which is probably close to the entire size of an ARM core just to do instruction decode (including the micro op cache and such).
I think you're forgetting we are dealing with one chip that is tiny, and another that is a giant in comparison.
I'm not certain why I feel compelled to explain this, but hopefully some others who read the thread will find it useful. Dynamic power consumption is one of those basic formulas that applies to all semiconductors. Die size is irrelevant thanks to the activity factor - it only plays a direct part when it comes to leakage. Basically, assuming that voltage and frequency were equal you can have a massive die with a 1 mF capacitance (just making numbers up) that's doing nothing except adding two numbers together and hence have an activity factor of .000001 and it would consume the exact same dynamic power consumption as a simple adder with a 1nF capacitance and activity factor of 1.
The same concept applies in this case - Haswell may have a lot of extra x86 baggage, execution units, and be just plain massive by comparison. But that only hurts it in terms of leakage power. When it comes to dynamic power only a fraction of the logic is actually toggling and expending energy... and it would be simply astounding if Intel needed to use even 25% more transistors*clocks to do the same work as an ARM design does. (That is to say that Intel may use more transistors, but it also would finish the work in fewer clocks which is all we're concerned about when talking dynamic power.)
Also, the "x86 overhead" is nowhere near as much as a penalty as some would like to make it out as being. Yes, it does add a small amount of die space to the actual CPU core, but it's really not much. Especially since what you're really concerned about is the delta between the x86 decode logic and what ARM processors have. Yes, just because the ARM ISA is simpler doesn't mean it doesn't have a considerable amount of logic here... there's a reason why A15 has 5 stages for fetch and 7 for decode, rename, and dispatch (for comparison Silvermont has 3 stages for fetch and 7 for decode, rename, and dispatch.)
Oh, and with respect to the continued claims that Intel is only able to obtain these extremely low operation voltages on a cherry-picked few dies that bin extremely well... Eh, unfortunately there's no publicly available information to dispel amusing notion. But if Intel can meet demand and continue to show strong margins then why precisely does it matter? Unless you wish to claim that the non-Intel-supplied systems that Anandtech reviewed are somehow using cherry-picked Haswell silicon.