witeken
Diamond Member
- Dec 25, 2013
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Eh, 16 FinFET has smaller SRAM cell sizes, so it is denser.
Since when is a 15% higher density in line with Moore's Law? (20/16)² = 1.6
Eh, 16 FinFET has smaller SRAM cell sizes, so it is denser.
Intel's process engineers just developed the best processes they could
show me TSMC's or Samsung's 28nm transistor with a 28nm half-pitch and gate.
20nm first metal layer pitch: 64nm.
Not even close to 20nm,
OK you want data about Intel upcoming 14nm so you all stop derailing the thread?
Here: http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/
http://electroiq.com/wp-content/uploads/2014/01/Chart-7.png
So it's 45nm metal pitch and 0.062 to 0.052um^2 of area, or in % numbers about 12 to 35% denser than TSMC 16nm node.
Possibly all the delays they had were because EUV went bad and to get the highest density they used 193i litho to the limits, also this increase over 0.09um^2 cell for 22nm is proven by the Broadwell die shots vs the Haswell ones (not in the link, Google it).
Of course the slide is two years old so something has changed, but still is the most relevant info about 14nm node. Wait two months to get all the updated infos at IDF.
K7 was more or less bought from NexGen, and K8 built on top of that.
I don't think K6 was crap at all