Question Binning and Yields question

[Hulk]

Do you think you have a better chance of getting better silicon towards the end of a production run for a line of chips rather than towards the beginning?

Here's my thought.

Let's take the Raptor Lake 8+16 die as an example. AFAIK it's binned as follows:
13900 (various designations)
13700
13600
13500?

Anyway let's say you were going to purchase a 13600K. This would be a die with at least 6 P's operational and 8 E's operational.
These would be binned K's, non numbered, and T's. Further complicating the issue is the fact that many of these parts will be artificially limited meaning operational cores fused off to make 6+8.

So in the beginning of the production run for this die all of the best parts are going KS, then K. After that all fully operational ones probably going non numbered and then T.

But as the yields get better and the SP rating of the silicon gets better I would assume the SP rating of the dies simply gets better on average.

So all of the best parts are going to be KS and they're all going to be really great. The 13900K's will get better just because they may actually have K's that could be KS's.

In fact, is it possible that some of the 13700K's could be really high SP rated with 8 E's fused off as the yields have gotten so good?

Do you think they were binning 13900KS parts right from the beginning or what is something like a few "tweaks" into the production run the machine that does the testing was logging some really great v/f curves and Intel noticed it?

Man I would love to see that binning data vs time for some dies.

Okay now have at me and let me know where I'm getting this all wrong/kind of right.

 

[Doug S]

TSMC has made public yield curves for pre risk production and risk production, so you can see the increase. No one officially releases yield information for production wafers, but often you can find 'rumors' that are probably pretty accurate.

It is safe to say that yield increases from early mass production to later mass production, though by how much depends on whether tweaks are constantly being applied during production (as Intel traditionally did and AFAIK TSMC does not or at least does not to the same extent Intel traditionally has)

 

[aigomorla]

No because you have no idea how the chip was boxes and packaged.
Ideally when the chip is cut, the best chips are in the center of the waffer.
Of course there will always be some exceptions to this, but in most cases the center chips had the best bins which we back in the days called cherries.

I think this had to do with how the silicon was formed and melted. The center of the waffer had the best physical properties as the sand was heated and made into that large chunk of glass, which is later cut and sanded to get the silicon waffer before its litho'd.

When intel did this, they would secure most of the center chips and package those separately to go to sponsored reviewers, over clockers, and demos. This is why a lot of people raged at sponsored reviewers because they could pull the near impossible feats with these cherry picked ES cpus.

I have had several of these cherry picked cpus thanks to my sponsor when i did a lot of kentsfield + yorktowns + gulftown validations. They were infact absolutely AMAZING, and intel always wanted them back if you managed to kill them.
Infact they promoted that you attempt to (in real working situations) kill it, and send it back with details on how you killed it, they rewarded you for doing so. They wanted to know what the weakest point was to patch it up for consumers.
(they would give you like 5 pre bin'd cpu's for every 1 you killed without doing something stupid.)
This is why the same chip always had revisions a while back ago.
Remember the Q6600 having 4-5 different revisions on the same chip but have amazing OC potential on each one.

But back to the main topic... the cherry bins are in the center.
You have no control at 2 stages where those chips are.
The third one can be done with you paying for return fee's, but its still a luck of draw.

1. the packaging of said chips after it leaves the validation machine.
2. the distribution site of where the packages are allocated and sold wholesale.
3. the final retail store which the chips then are sold to consumers.

Meaning the chips are shuffled three times regardless like shuffling the deck of cards 3 times, before you get to pull the card draw.
Meaning it will be a MAJOR luck of the draw, unless your like dell and buy entire wafers of cpu, or pallets from intel direct.
Or your best buddies with RnD and Marketing, and they can get the cherry bin's direct after cutting from the fab's.

We used to ask what bin numbers the great overclocking chips had, and people used to hunt down bin numbers for those chips as it would tell you which bin numbers were the center cut wafers.
But i do not know if this applies anymore, as i have stepped out of the game a long while ago.

 

[solidsnake1298]

I SERIOUSLY doubt that the v/f data would ever be made public. That seems like something that would be a very closely held secret by any foundry.

It is my understanding that the best dies from a wafer are those in the center (this applies to CPUs, GPUs, and RAM). And those center dies are almost exclusively used in workstation/enterprise parts because of their superior v/f curves and higher reliability. Why sell a top notch CPU die for $500 to some gamer plebs when we can sell that same die to Amazon for $1500. Or $1500 for a GPU die to a sweaty gamer when we can sell it to Pixar for $10000.

With chiplets, boosting, and whatnot there are more ways for AMD/Intel/Nvidia to bin and segment their parts than was possible in the past. For example: TSMC produces a flawless 8 core Zen 4 CPU die. But it isn't able to achieve the boost clocks of the 7950X SKU. Instead, they put in the single CCD 7700X SKU which has lower boost clocks. Another has a flaw in a couple cores, but can achieve good boost clocks? It becomes one of the 7900X CCDs.

Back in the day, some 1U server CPUs shared the same socket as their pedestrian desktop CPU cousins. It wasn't uncommon for dedicated OCers to buy said server CPUs and overclock the snot out of them. Socket 939 AMD Opteron 100's anyone? The Opteron 165 had a base clock of 1.8Ghz. Most people were able to achieve, at least, 2.7Ghz. Some top binned 165's could reach 3.0Ghz (I was one of these lucky few).

Alas. With the sharp market segmentation between desktop and enterprise parts, no shared sockets, those days are long gone.

 

[aigomorla]

And those center dies are almost exclusively used in workstation/enterprise parts because of their superior v/f curves and higher reliability. Why sell a top notch CPU die for $500 to some gamer plebs when we can sell that same die to Amazon for $1500. Or $1500 for a GPU die to a sweaty gamer when we can sell it to Pixar for $10000.

This is why back in the days people swore on Opty and Xeons when overclocking more so then Athlons and Core2Quads. They were all the same wafer and then allocated differently.
But then AMD and Intel started locking cpu's and custom FSB + BCLK + QPI could no longer be tuned and we were then stuck with straight multipliers.

But yes, your right, it was common knowledge that the server chips would be better bin'd hence why old school overclockers went after those Workstation CPU's when we were allowed to overclock them on overclocking boards.

But now enterprise chips are not made from the same wafer as consumer chips like they used to.
So the OP is probably asking if there is any way to control the odds of getting one of those center wafer consumer chips.

 

[solidsnake1298]

So the OP is probably asking if there is any way to control the odds of getting one of those center wafer consumer chips.

In a word: Yes. In more than a word: The KS is the better bin. Intel knows its the better bin and charges a premium for it. On the AMD side, the X SKU's are the better bins. The Ryzen 9 SKUs with higher boost clocks are the better bins.

AMD and Intel are onto us overclockers. The jig is up. If a die meets the spec for a higher SKU, it will go in that SKU. The days of top tier binned chips going in lower SKUs are gone. AMD and Intel have gotten so good at binning and product segmentation that "Golden chips" aren't really a thing anymore. The 7950X is the golden chip. The 13900KS is the gold chip. From what I've seen, the closest thing to a golden chip these days is a CPU that will undervolt a bit more than average. Or will achieve a slightly higher FCLK/memory OC (assuming the RAM isn't the limiting factor).

I forget which of the top tier overclockers it was (derbauer?), but when selecting which CPU they will use for their world record runs they will test 100+ CPUs and select the 4 or 5 that are something like 5% faster for further testing. AMD and Intel have gotten so good at automatically redlining their CPUs in a stable manor from the factory that CPU overclocking is barely a thing for us mere ambient cooling mortals.

 

[Hulk]

Great information here. Thank you.

Let me be more precise with my questions.

1. I understand that generally the best parts come from the center of the wafer because there is more homogeneity in this area, that makes sense. But wouldn't the final decision for the packaging for each die be determined by testing after packaging, not wafer location?

I think the point you are making is that after packaging and testing it is found that the best dies generally come from the center of the wafer, correct?

The testing must be quick and accurate. Obviously Intel isn't running prime 95 for hours at various voltages and frequencies!! I'm kidding of course but they must be able to determine v/f curves for each core in a die in seconds to send it to the proper bin.

2. My initial question can be boiled down as follows. Lets assume a particular CPU model is in production for 2 years (arbitrary number I have no idea). Do you think your chances of getting a high SP part are better at the end of the run as opposed to buying upon release of the part?

 

[solidsnake1298]

2. My initial question can be boiled down as follows. Lets assume a particular CPU model is in production for 2 years (arbitrary number I have no idea). Do you think your chances of getting a high SP part are better at the end of the run as opposed to buying upon release of the part?

Sample size of 2, so take this with a grain of salt. I got my last CPU, a Ryzen 2700X, late in the 2000 series' life cycle. It did not perform any better than the benchmarks I saw at its launch. Single threaded or multi-threaded. Same with my current CPU, a Ryzen 5900X. I bought it new, but on sale, this past December. It also performs the same as the initial benchmarks. Reading reddit, here, Youtube, tech tubers, etc., I have not seen anything about...performance creep, I guess you could call it? Due to process/yield improvements.

 

[SK10H]

The testing must be quick and accurate. Obviously Intel isn't running prime 95 for hours at various voltages and frequencies!! I'm kidding of course but they must be able to determine v/f curves for each core in a die in seconds to send it to the proper bin.

The latest CPU quality has very little room for error when it's factory clocked nearly to the max compare to the past. It depends on the % of people who test on p95 small fft and then go ahead and ask for RMA.

I wonder if any reviewer has been been invited in the past on a tour to show how this is done? Not talking about just the factory clean room, but more like the actual testing and validation part showing the die attachment where the general public is allowed to see. What does the industrial grade testing heatsink look like, show me how it's attached during testing, thermal grease they use etc? m

 

[solidsnake1298]

@SK10H - LTT got to tour Intel's Israel fab.

 

[SK10H]

@SK10H - LTT got to tour Intel's Israel fab.

As was mentioned at the end of the video, this is more like a manufacturing tour than a QA/binning tour, so we don't get to see how they did the final testing and the amount of time needed to verify the v/f curve.

 

[aigomorla]

2. My initial question can be boiled down as follows. Lets assume a particular CPU model is in production for 2 years (arbitrary number I have no idea). Do you think your chances of getting a high SP part are better at the end of the run as opposed to buying upon release of the part?

There again is no way we can answer that because of the third point i stated.
Assume you have 2 newegg distros. (Las Vegas + North Carolina)
One is constantly filling orders for CPU of X and not Y, while the other is filling orders for Y and very little X.
So Y is getting stacked, and keeps getting pushed behind the shelf, as X is on the other distro.
3 yrs pass, and Y still hasn't picked up, and is sitting at the rear of the shelf.
CPU becomes EOL and newegg goes though inventory clearance, and finds CPU Y.
CPU Y is being sold late but the distro got it early, because another distro was filling orders for Y while this distro filled orders for X.

So there is no way you can assume on release.
Also Intel could of stock piled the CPU and did a control release, and realized oh no we getting spanked by AMD... flood the gates with more CPU's @ 2/3rd the cost.
Stockpile opens, and you get another infusion of god knows which batch of chips.

There is no way to determine that.
Anytime you shuffle one of the 3 points i stated, its all lottery all again.

Also just to note.... higher tier chips do not mean higher bin'd chips.
Intel has a machine which they plug in and can ballpark oh this chip can handle this, while this cant.
Typically if it can handle better thresh hold it is a better chip, but.... and i stress BUT, its very cut and dry.
Meaning, if it can just get past X, its a 13900KS, they wont try X + 1 or 2 or 3.
And sometimes if they have too much X + 1 or a X + 2 for quota, that chip may become a 13600K.
So because a chip is a 13900KS (unless its like a 8086 special edition), typically it wont gaurentee your odds at the silicon lottery.

Because intel could of had an awesome wafer they cut at the middle of the crystal, by some fluke of nature the geomagnetic alignment of the earth core allowed a miracle mixture in the hot pot, and the silicon crystals magically aligned and they got X+9000 chips. They are not going to make ALL the chips in that wafer into 13900KS.

But if i recall chips now a days do not have disabled cores or inactive cores.
So i think an entire wafer is dedicated to one class of chips, and it is cut from there, or at the very least specific sections are dedicated and its cut from there.
And seeing how die sizes are all over the place, no fab can afford to dedicate the entire center zone to flag ship chips, as it will be a horrible way to play tetris so to speak when doing the lith on them afterwards, and makes cutting an absolute nightmare.

 

[Doug S]

It is my understanding that the best dies from a wafer are those in the center (this applies to CPUs, GPUs, and RAM). And those center dies are almost exclusively used in workstation/enterprise parts because of their superior v/f curves and higher reliability.

That is completely wrong. Silicon wafers are cut from single crystal boules, there is no difference in properties between inside and outside regions. What you suggest would be impossible anyway because a wafer is (except in cases for small runs using so-called single project wafers) composed of the same dies. Intel isn't putting Xeons on the inside of a wafer and Celerons on the outside.

 

[Kocicak]

The same reticle containing a single chip (or even part of a single chip?) is projected on a monocrystal (homogeneous - everywhere the same) wafer the same way every time, the wafer travels. The chips on the wafer are the same all over the wafer, some are just incomplete - they could not fit on the wafer.

There are however other processes during manufacture at play, they spread various layers of masks on the wafer, they etch it, etc, and in theory there could be some variance in the distribution of chips in term of their quality on the wafer. But I imagine they do whatever they can to avoid that.

 

[Hulk]

Okay let me ask the question one more time with even more specificity.

If you could somehow view the SP data of every 13700K that Intel produced in chronological order would the moving average of this number increase? Decrease? Remain constant? Or randomly fluctuate?

Never mind it being impossible to get. I understand that.

 

[solidsnake1298]

Okay let me ask the question one more time with even more specificity.

If you could somehow view the SP data of every 13700K that Intel produced in chronological order would the moving average of this number increase? Decrease? Remain constant? Or randomly fluctuate?

Never mind it being impossible to get. I understand that.

Currently, I would say it would remain constant, within a margin of error.

That is completely wrong. Silicon wafers are cut from single crystal boules, there is no difference in properties between inside and outside regions. What you suggest would be impossible anyway because a wafer is (except in cases for small runs using so-called single project wafers) composed of the same dies. Intel isn't putting Xeons on the inside of a wafer and Celerons on the outside.

The raw wafer, sure, is uniform. But, post lithography, the outer regions are less perfect since they are off axis from the UV/EUV source. But, you are correct that Intel doesn't use the same dies across product lines. But Ryzen and Epyc do share dies. Sometimes I forgot that the world doesn't revolve around AMD....

 

[Doug S]

Currently, I would say it would remain constant, within a margin of error.


The raw wafer, sure, is uniform. But, post lithography, the outer regions are less perfect since they are off axis from the UV/EUV source.

What? The light source isn't sitting over the center of the wafer. I managed to find a nice image from ASML that illustrates what is going on. I knew it used mirrors but holy cow that's a lot of mirrors!

 

[aigomorla]

But, you are correct that Intel doesn't use the same dies across product lines.

Well they sort of do.

For example, The Xeon E3 v5 and v6 family is essentially the same CPU as the 7000 and 9000 series.

It just allows ECC to run on server boards, but are essentially i believe the same cut die.
So there is selective binning involved to some degree.
But i think its still more practical to cut out entire dies of same CPU instead of grade binning them for Xeons and Desktops.

 

[zir_blazer]

Well they sort of do.

For example, The Xeon E3 v5 and v6 family is essentially the same CPU as the 7000 and 9000 series.

It just allows ECC to run on server boards, but are essentially i believe the same cut die.
So there is selective binning involved to some degree.
But i think its still more practical to cut out entire dies of same CPU instead of grade binning them for Xeons and Desktops.

Xeon E3 1200v5 and 1200v6 are Skylake (6xxx) and Kaby Lake (7xxx) generations. It was later renamed to Xeon E 2xxx for Coffee Lake. Also, what Intel does with the Xeon E3 line is roughly the same thing than AMD did during the old days of Socket 939 Opterons. Same socket and everything, but with UDIMM ECC support and Server/Workstation oriented boards.
S939 Opterons were known to clock around A64 FX levels. In the case of Xeons E3, it is impossible to known due to the locked Multipliers and poor Base Clock overclock support. I think only for a brief time than it was possible to do Base Clock overclock in non-K Skylake (Thus Xeon E3 1200v5), but I don't recall than there was a consensus if they were better overclockers because they weren't really popular to begin with. Also, in that same generation Intel decided to stop allowing usage of Xeons E3 on consumer boards, so you needed a C232/C236 board with Base Clock overclock support, which was a super small niche.