bitsandchipsAMD Reveals the Monsterous ‘Exascale Heterogeneous Processor’

[ShintaiDK]

Its a research paper, they dont plan any SKU.

 

[AtenRa]

Thats why I wrote the current edition. But its unlikely that it will change for retail.

Call of Duty Ghost/Armoured Warfare, Watch Dogs and Witcher 3 also list 6GB as minimum for example.
http://store.steampowered.com/app/292030/
http://store.steampowered.com/app/209160/
http://store.steampowered.com/app/209650/
http://store.steampowered.com/app/243470/

And I am sure I could find more.



But there is, better research next time

yeap, you better dont read to much on those specs

 

[ShintaiDK]

yeap, you better dont read to much on those specs

You know there is more to it than just some random time in a game? Also how much was paged, how did the game behave?

Minimum is there for a reason. And they set it as low as possible for maximum sales.

 

[Fjodor2001]

Its a research paper, they dont plan any SKU.

It's a research paper which of course has the purpose of evaluating future potential SKUs. And that research paper is just about the specific server APU config mentioned in the OP. We already know AMD is working on other actual SKUs with Zen CPU cores, with and without iGPU & HBM for both desktop and server, soon to be released.

Stop ruining the discussion by bitching about meaningless details which are obvious to everyone anyway.

 

[Phynaz]

Its a research paper, they dont plan any SKU.

This is the part he doesn't get.

 

[Dresdenboy]

BTW, AMD already published about that stuff in 2014, and filed many related patents.

 

[Fjodor2001]

This is the part he doesn't get.

Read my previous post. If you don't get that, you're beyond hope.

 

[mrmt]

Just look at the research paper in the OP, where they plan SKUs with 32 GB HBM. Now that is for server use of course and totally overkill for desktop, but eventually it trickles down to desktop too if/when need arises.

Did you look at the paper? No, you didn't, and it seems that neither did the clowns at bits and chips. AMD doesn't talk about Zen cores and in the case of the memory, they explicitly say that they will not use HBM for this concept. And they don't mention products roadmap at all.

Looks like Fuzdzilla got strong competition.

 

[Fjodor2001]

Did you look at the paper? No, you didn't, and it seems that neither did the clowns at bits and chips. AMD doesn't talk about Zen cores and in the case of the memory, they explicitly say that they will not use HBM for this concept. And they don't mention products roadmap at all.

Looks like Fuzdzilla got strong competition.

The article is not free for the public. The abstract is though, and that does not say HBM will not be used. What in the full article specifically says HBM will not be used?

Also, are you're expecting AMD to develop a new uArch in parallel with Zen and also introduce a new HBM-like memory in parallel with the exiting HBM? Really? You think that is realistic?

 

[mrmt]

The article is not free for the public. The abstract is though, and that does not say HBM will not be used. What in the full article specifically says HBM will not be used?

Maybe you should pay for it and discover for yourself?

Also, are you're expecting AMD to develop a new uArch in parallel with Zen and also introduce a new HBM-like memory in parallel with the exiting HBM? Really? You think that is realistic?

AMD currently develops two architectures in parallel, as their ARM development isn't yet canned. Plus for such a product to be engineered in the next 4 years AMD would have to freeze the concept as of now, and not wondering about which research path they will pursue in order to reach a viable product. It's an exascale product, do you think AMD will reach exascale levels of performance in the next 4 years?

 

[Fjodor2001]

Maybe you should pay for it and discover for yourself?

If someone makes a claim, the burden of evidence is upon him. I didn't make the claim, you did. Ask yourself for the proof.

AMD currently develops two architectures in parallel, as their ARM development isn't yet canned. Plus for such a product to be engineered in the next 4 years AMD would have to freeze the concept as of now, and not wondering about which research path they will pursue in order to reach a viable product. It's an exascale product, do you think AMD will reach exascale levels of performance in the next 4 years?

So you think the chip in the OP has an ARM based CPU core targeting exascale performance? Really?

 

[Sweepr]

I didn't make the claim, Sweeper did. Ask him for the proof.

Where?

 

[Fjodor2001]

Where?

Sorry, I meant mrmr. Your posts are awfully alike.

PS. I updated my previous post to reflect that now.

 

[mrmt]

If someone makes a claim, the burden of evidence is upon him. I didn't make the claim, you did.

Who was talking about upcoming zen APU?

 

[Phynaz]

Read my previous post. If you don't get that, you're beyond hope.

I did read your post. You still don't get it.

Feel better that you attacked me?

 

[Fjodor2001]

I did read your post. You still don't get it.

Feel better that you attacked me?

Whenever you enter a thread on this forum it's only to start an argument. You never bring any info or technical details of value. I'm done with you. Keep trolling if you want to.

 

[Fjodor2001]

Who was talking about upcoming zen APU?

We're talking about the potential APU mentioned in the OP. You said it will not use Zen CPU cores and not HBM. Got any source for those claims?

 

[Phynaz]

Whenever you enter a thread on this forum it's only to start an argument. You never bring any info or technical details of value. I'm done with you. Keep trolling if you want to.

Hahaha. Thanks.

 

[Dresdenboy]

Its a research paper, they dont plan any SKU.

Mark Papermaster wrote:

The goal of the research is eventual commercial applications, so the IP created as part of this research will make its way into various future AMD products.

[...] R&D for technologies targeted for commercial use in in the 2020-2023 timeframe

https://community.amd.com/community...res-third-consecutive-exascale-research-grant

https://asc.llnl.gov/fastforward/AMD-FF.pdf also mentions the use of technologies and tools developed in those DOE research programs in products.

And if one cares to look what happened before that single AMD slide - see, all your friends are in there :

• AMD will conduct research for an integrated exascale node architecture. Particular areas of emphasis include near-thresholdvoltage logic and other low-power computing technologies. AMD will investigate a new standardized memory interface
• Cray Inc. will explore alternative processor design points, including ARM microprocessor designs.
• Intel will use this award to continue to advance research in energy efficient node and system architectures, including software targeted at developing extreme-scale systems.
• NVIDIA will build on its work in FastForward 1, with a strong focus on energy efficiency, programmability, and resilience.
• IBM will investigate next-generation standardized memory interface.

http://science.energy.gov/~/media/a...1121/2014_ASCAC_Harrod_Exascale_Update_v2.pdf

An older roadmap has a node prototype milestone set at the beginning of 2019:
http://www.eetimes.com/document.asp?doc_id=1324606
The Exascale prototype is scheduled for 2023. These dates have been set back by a year already as an older roadmap shows here: http://www.hpcwire.com/2014/04/07/doe-exascale-roadmap-highlights-big-data/

Some of the people involved there:
Mike Schulte is responsible for things like "Advanced reliability and resiliency mechanisms" (redundant multithreading etc.)
Mike Ignatowski is responsible for memory tech. I think, buletaja and jeff_rigby mentioned him in the AMD CEO blabla thread as one guy responsible for some XBox 1 memory stuff.

Memory.. there we'll see topics researched (and patented) like in memory computing (PIM), swapping less used pages out to NVRAM (RRAM, PCRAM, etc.), and so on.

PIM cores could be anything, like ARM Cortex-A5, FPGA, GPGPU:
http://wwwi10.lrr.in.tum.de/~weidendo/uchpc14/slides/kavi_uchpc14.pdf

How about large (<=1GB) DRAM based L4 caches:
http://research.cs.wisc.edu/multifacet/papers/ieeemicro12_missmap.pdf

More here:
http://www.amd.com/en-us/who-we-are...#journal-conference-and-workshop-publications

 

[Excessi0n]

yeap, you better dont read to much on those specs

How does that refute a 6GB minimum memory requirement? The Witcher devs are smart enough to realize that there is, at an absolute minimum, an OS running in the background. The game itself might use ~4 gigs, but that doesn't mean you can run it on a system with 4 gigs of memory. Things get worse when you postulate unified memory, where it will consume additional memory for all of the things that VRAM gets used for.

2 gigs of VRAM use at 1080P is also pretty optimistic. My cards have that much and I max out the memory all the time at that resolution. Two years from now...

If you aren't gaming then 8GB of HBM would be more than enough but, in that case, why are you using a fancy-pants APU with a bunch of on-package stacked memory?

 

[mrmt]

We're talking about the potential APU mentioned in the OP. You said it will not use Zen CPU cores and not HBM. Got any source for those claims?

If you think I'm going to post on an open forum content from a paid, closed source just to quench your curiosity, don't hold your breath, instead you can just read Papermaster's post on AMD website that Dresdenboy graciously provided:

https://community.amd.com/community...res-third-consecutive-exascale-research-grant

This is part of the DOE FastForward 2 program, which seeks to fund innovative new and/or accelerated R&D for technologies targeted for commercial use in in the 2020-2023 timeframe. AMD’s FastForward 2 research will focus on node architecture based on our HSA-based APUs, and for a new generation of memory interfaces.

AMD will be in real trouble if they are thinking about HBM and Zen products by 2023. Exascale computing will demand a very different set of technologies than we have today, and this paper is the product of a research grant of the US government, as far as I am aware the US government isn't paying for the development of CPUs today.

 

[ZaphodBbrox]

Journal article from AMD on exascale, for those with access..

http://ieeexplore.ieee.org/xpl/arti...umber=7155462&filter=AND(p_IS_Number:5210076)

Abstract: This article provides an overview for AMD's vision for exascale computing, and in particular how heterogeneity will play a central role in realizing this vision. Exascale computing requires very high levels of performance capabilities while staying within very stringent power budgets. Hardware optimized for specific functions is much more energy efficient than implementing those functions with general purpose cores. However, there is a strong desire for supercomputer customers to not have to pay for custom components designed only for high-end HPC systems, and therefore high-volume GPU technology becomes a natural choice for energy-efficient data-parallel computing. To make fully realize the capabilities of the GPU, we envision exascale compute nodes comprised of integrated CPUs and GPUs (i.e., accelerated processing units or APUs) along with the hardware and software support to enable scientists to effectively run their scientific experiments on an exascale system. We discuss the hardware and software challenges in building a heterogeneous exascale system, and we describe on-going research efforts at AMD to realize our exascale vision.

 

[antihelten]

We're talking about the potential APU mentioned in the OP. You said it will not use Zen CPU cores and not HBM. Got any source for those claims?

If you wan't access to the paper without paying for it, you could try your local university library.

Anyway with regards to the things mrmt mentioned, the paper doesn't make any mention of the specific nature of the CPU, other than to say that they would be optimized for single threaded performance, and that they could be either x86 or ARM. With regards to HBM, they mention that HBM cannot provide the necessary capacity (1TB/node), so instead they will use some alternative 3D stacked DRAM with a total capacity of 128GB (from 8 stacks) plus DDR4 for the rest. The nature of this 3D DRAM is not mentioned, but it sounds a bit like HBM2 imho.

 

[Fjodor2001]

If you wan't access to the paper without paying for it, you could try your local university library.

Anyway with regards to the things mrmt mentioned, the paper doesn't make any mention of the specific nature of the CPU, other than to say that they would be optimized for single threaded performance, and that they could be either x86 or ARM. With regards to HBM, they mention that HBM cannot provide the necessary capacity (1TB/node), so instead they will use some alternative 3D stacked DRAM with a total capacity of 128GB (from 8 stacks) plus DDR4 for the rest. The nature of this 3D DRAM is not mentioned, but it sounds a bit like HBM2 imho.

Thanks for the tip. It would be nice to have access to the complete article, but I was primarily looking for at least some quotes confirming the claims that were made. Because so many people on this forum make claims that they have no source for and in the end turns out to just be made up. So if there if controversial statements are made, I like to see some evidence before accepting them as fact. That's all.

Anyway, as I understand it research paper is not specific about what CPU and memory is to be used in an actual future product. But the final product may use a HBM successor such as HBM2, and potentially also x86 cores such as Zen (or a successor). I wonder if it was the fact that it was AMD that published the research paper that made the article in the OP make those assumptions? After all, for AMD those would be the most logical choices.

 

[coercitiv]

But the final product may use a HBM successor such as HBM2, and potentially also x86 cores such as Zen (or a successor).

There is no final product! It's been said again and again on this thread: don't discuss a research paper as if it's specs for a product.