i thought bulldozer was to "break down the walls" so single threaded applications would get a large speed boost...
Here's the thing. How much do you realistically think AMD can change in the next 2 months? Yes, it really looks like the chip is crippled and broken, but I don't think the crippling is intentional. It seems like the chip really has a lot that needs to be fixed/improved, but AMD has a very short timeframe in which to do it. The benchmark results right now are horrendous for a chip that's supposed to compete with 2500K, 2600K, and Ivy Bridge when it comes out early next year.
In contrast, Intel's Sandy Bridge ES chips benchmarked pretty close to the final versions, and Anandtech ran those benchmarks 3-4 months before the official release of SB chips (August 2010). Here we are 3 months away from Bulldozer's "official" release and AMD still can't produce engineering samples that can perform half-decently?
Sandy Bridge is a completely new microarchitecture, not a die-shrink. Nehalem was the architecture for the first gen Core i3/i5/i5 chips, and Wolfdale was the 32nm die-shrink. Next year, Ivy Bridge will be the die-shrink of Sandy Bridge.
This is why it's depressing news that AMD cannot get decently performing ES chips out just a few months before release, when Intel was able to do the same 3-4 months before the final SB release.
Sandy Bridge ES chips 3-4 months before release were performing exactly on par with their final retail counterparts.
See the difference?
Sandy Bridge might not have been a completely new architecture (arguably no microarchitecture is completely new), but it was a complete redesign. It was not an incremental update to Nehalem.Um, SB is not a completely new uarch. It is an enhancement of nehalem.
Hell, if you wanna get technical, SB, nehalem, C2D all pretty much get their roots from the p6 uarch.
Sandy Bridge might not have been a completely new architecture (arguably no microarchitecture is completely new), but it was a complete redesign. It was not an incremental update to Nehalem.
...We are beyond original launch date...
Sandy Bridge is a completely new microarchitecture, not a die-shrink. Nehalem was the architecture for the first gen Core i3/i5/i5 chips, and Wolfdale was the 32nm die-shrink. Next year, Ivy Bridge will be the die-shrink of Sandy Bridge.
This is why it's depressing news that AMD cannot get decently performing ES chips out just a few months before release, when Intel was able to do the same 3-4 months before the final SB release.
Um dude, it was a very incremental design. They added AVX and took out the ROB and put a PRF in its place also added trace cache, tacked on a crappy GPU. Made a few other tweaks here and there, other than that, its pretty much unchanged from nehalem.
Sounds just like the 'Reverse Hyper Transport' Rumor from the AM2 launch.
This is hilarious because people actually believe that BD will perform like this POS ES.
No. You obviously have no idea what you're talking about.
List of changes:
- Reintroduction of trace cache (this is actually big!)
- L3 cache latency reduced; now not part of the uncore, so it runs at full speed (this is also huge!)
- Branch predictor is new
- AVX
- PRF added
- Load/Store buffers increased in size
- Ring bus (really nice if you want to scale # of cores)
- on-die graphics...
- ROB buffers increased from 128 to 168
Just wondering, why doesn't AMD switch to using an LGA for their sockets? Is it just to keep backwards compatibility with AM2/AM3? Or is it cheaper/easier to manufacture, or something?
No. You obviously have no idea what you're talking about.
List of changes:
- Reintroduction of trace cache (this is actually big!)
- L3 cache latency reduced; now not part of the uncore, so it runs at full speed (this is also huge!)
- Branch predictor is new
- AVX
- PRF added
- Load/Store buffers increased in size
- Ring bus (really nice if you want to scale # of cores)
- on-die graphics...
- ROB buffers increased from 128 to 168
David Kanter said:Sandy Bridge is a fundamentally new microarchitecture for Intel. While it outwardly resembles Nehalem and the P6, it is internally far different. The essence of an out-of-order microarchitecture is tracking, re-ordering, renaming and dynamically scheduling operations to achieve the limit of data flow. Nehalem and Westmere rely on the same mechanisms that date back to the original P6. Sandy Bridge changes the underlying out-of-order engine and uses the more efficient approach taken by the EV6 and P4. That one change alone qualifies Sandy Bridge as a different breed entirely from the P6. But, there are changes in almost every other aspect of the design. The uop cache is a huge improvement for the front-end, largely by eliminating many of the vagaries of x86 fetch and decode. The implementation is quite clever and achieves many of the aims of the P4s trace cache, but in a far more efficient and reliable manner. AVX improves execution throughput and most importantly, the more flexible memory pipelines benefit almost all workloads.
Um dude, it was a very incremental design. They added AVX and took out the ROB and put a PRF in its place also added trace cache, tacked on a crappy GPU. Made a few other tweaks here and there, other than that, its pretty much unchanged from nehalem.
Well, my bad =P I didnt think it was that much different. Just pick and choose parts from P4 and P6 and integrate them into one thing. Hence why I dont see it as a big change. OTOH, stars -> BD is a much more drastic change. Hardly anything in BD represents any uarch of AMD's past, much less a normal x86 design. To me, thats a true redesign.
I think it's reasonable to believe that the final retail BD will be in the same ballpark. AMD's obviously working to fix and improve it, but it's not like the final retail product will perform an order of magnitude better...
A big part of the performance improvements will come from the much higher clock speed on the retail Bulldozer chips (>3.5 GHz vs. 2.8 GHz), but clock for clock I'm not expecting more than a ~10% improvement from this ES.
Ok so SuperPi isn't AMD's strongest benchmark, but you're saying you believe that BD will be even slower than old Athlon X2 processors? LOL.
It's crippled for a reason, because people just like the guy from ChipHell who somehow gets their hands on an engineering sample and doesn't follow NDA and wants to benchmark it. Do you think AMD wants that to happen?
It's said that the es sample is from foxconn, and was sold online, so I believe the owner is free to post the info on forums, there really is no NDA for him to follow.
Well, if you break down the Bulldozer changes into a list, would it really look much different?
- Widened decode width to 4
- Added scheduling support for two threads
- Added PRF
- Decreased ALUs and AGUs to two dedicated ones per thread
- Added AGU capability for simple ALU instructions
- Split FPU into two halves which can be assigned to different threads
- Added AVX support
- Added FMA4
What about these things makes it a unique new microarchitecture?