Bulldozer ES benchmark is out!

[AdamK47]

Super Pi? Really, Super Pi? Why do these Asian sites refuse to use a competent benchmark? May as well run CPUMark 99.

 

[996GT2]

Super Pi? Really, Super Pi? Why do these Asian sites refuse to use a competent benchmark? May as well run CPUMark 99.

Disregarding the fact that the site also tested with Cinebench R11.5, what's wrong with Super Pi as a measure of single threaded performance?

My old Pentium 4 @ 2.8 GHz did 1M in about 45 seconds
My Athlon 64 3500+ @ 2.8 GHz did 1M in about 32 seconds
My Core 2 Duo T8300 @ 2.4 GHz did 1M in about 21.5 seconds
My 2500K @ 5 GHz does 1M in around 7.5 seconds.

That shows a pretty good correlation between better single thread performance and super pi 1M times.

 

[Arachnotronic]

Well, to be fair, Nehalem rocks so hard that a "redesign" isn't going to be as drastic as a redesign of Stars which is...lacking.

 

[Skurge]

Disregarding the fact that the site also tested with Cinebench R11.5, what's wrong with Super Pi as a measure of single threaded performance?

My old Pentium 4 @ 2.8 GHz did 1M in about 45 seconds
My Athlon 64 3500+ @ 2.8 GHz did 1M in about 32 seconds
My Core 2 Duo T8300 @ 2.4 GHz did 1M in about 21.5 seconds
My 2500K @ 5 GHz does 1M in around 7.5 seconds.

That shows a pretty good correlation between better single thread performance and super pi 1M times.

I think people treat it like 3d mark for the same reasons. It doesn't really represent real world performance.

 

[996GT2]

Well, to be fair, Nehalem rocks so hard that a "redesign" isn't going to be as drastic as a redesign of Stars which is...lacking.

If only Stars came out in 2006...then it would have been great!

 

[Joseph F]

Sandy Bridge is based on a completely new microarchitecture. It's not a die-shrink; that was Nehalem-->Wolfdale.

Sandy Bridge's development started in ~2005, which is about the same time development on Bulldozer began as well.

Wolfdale was not a die-shrink of Bloomfield. (i7 900 series) Wolfdale was a die-shrink of Conroe (C2D) with more L2 cache.

 

[hamunaptra]

Disregarding the fact that the site also tested with Cinebench R11.5, what's wrong with Super Pi as a measure of single threaded performance?

My old Pentium 4 @ 2.8 GHz did 1M in about 45 seconds
My Athlon 64 3500+ @ 2.8 GHz did 1M in about 32 seconds
My Core 2 Duo T8300 @ 2.4 GHz did 1M in about 21.5 seconds
My 2500K @ 5 GHz does 1M in around 7.5 seconds.

That shows a pretty good correlation between better single thread performance and super pi 1M times.

Its pretty meaningless nowadays to do cross cpu comparisons with it cuz it uses x87 which is outdated and hardly anything uses it anymore. Its only good for comparing a cpu to the same cpu different clock speed.

Manufacturers of current CPU's could give a rats behind about x87. SSE and everything above it is what is used nowadays.
Im sure if either AMD or intel wanted, they could design dedicated hardware for specific x87 code and go at it in superpi lol! But...people use more than superpi for their PC's...

 

[996GT2]

Wolfdale was not a die-shrink of Bloomfield. (i7 900 series) Wolfdale was a die-shrink of Conroe (C2D) with more L2 cache.

I meant to say Westmere

 

[Idontcare]

Super Pi? Really, Super Pi? Why do these Asian sites refuse to use a competent benchmark? May as well run CPUMark 99.

Given that you can run superPi on a rig that is practically unstable and useless to try and get through much else, I've always assumed peeps do sPi 1M on ES rigs because the rig is so buggy and unstable that it is likely to crash if stressed with doing too much more.

There's a reason it is the suicide-benchers bench of choice!

 

[Bearach]

Disregarding the fact that the site also tested with Cinebench R11.5, what's wrong with Super Pi as a measure of single threaded performance?

My old Pentium 4 @ 2.8 GHz did 1M in about 45 seconds
My Athlon 64 3500+ @ 2.8 GHz did 1M in about 32 seconds
My Core 2 Duo T8300 @ 2.4 GHz did 1M in about 21.5 seconds
My 2500K @ 5 GHz does 1M in around 7.5 seconds.

That shows a pretty good correlation between better single thread performance and super pi 1M times.

The two bolded parts are not useful in this demonstration. They would need to be the same clock speed as the previous two (2.8GHz) to be feasible for what you're trying to show.

Back on topic though, I don't think SuperPi is great for testing new processor architectures. Nor is it good for testing the full performance a processor offers... Having said that, I hope that this ES is a flaky one cause it looks weak to me.

 

[HilbertSpace]

http://www.hardwarecanucks.com/news/cpu/llano-benchmarks-found-online/ -

Looks even slower in Cinebench - when comparing to Phenom (in Anandtech Bench) it's slower - doesn't look right to me.

- sorry - this is for Llano...

 

[Idontcare]

Beta hardware is beta and not gamma (production) for a reason.

If everything was sunny and rosy with bulldozer (including the platform) then it would be launched already.

There's a reason it ain't. And there's a reason a new stepping is involved...they don't spend money doing respins for the heck of it.

 

[nonameo]

Beta hardware is beta and not gamma (production) for a reason.

If everything was sunny and rosy with bulldozer (including the platform) then it would be launched already.

There's a reason it ain't. And there's a reason a new stepping is involved...they don't spend money doing respins for the heck of it.

Personally, I'm more concerned about llano. I don't see AMD ravaging intel in desktop performance or server performance, but I can see them making some headway in the mobile space.

 

[3DVagabond]

Beta hardware is beta and not gamma (production) for a reason.

If everything was sunny and rosy with bulldozer (including the platform) then it would be launched already.

There's a reason it ain't. And there's a reason a new stepping is involved...they don't spend money doing respins for the heck of it.

What I've been able to gather from reading around (and it's all unconfirmed rumor and speculation) is that BD isn't clocking as high as they want. It, apparently, can hit the 3.8 w/4.2 turbo, but there's not enough O/C headroom for their liking (We all know how high SB can go. Up to 5GHz.) There's also talk of low yields.

Assuming there's truth to this, then it can be that AMD has taken the BD they already have (less than what they want to have due to lower yields) and decided to use them for server chips, where O/C'ing isn't needed, and have done a respin to improve O/C'ing headroom for the desktop models.

All conjecture, but is a reasonable explanation. If BD is as bad as some are thinking I would have to believe that AMD would have redesigned, or scrapped it, long ago.

 

[podspi]

Bleh. I can't believe 'overclocking' is a feature now.

 

[intangir]

Add to that -

Improved prefetch
Drastically improved branch predictors
Drastic revamp of entire cache hierarchy
Many sections of the pipelines decoupled from the others
The fact there is sharing of very specific parts of uarch and other parts not. Stars shares...what the L3?

On paper the core and fundamentals BD uarch looks NOTHING like stars.
This cant be said of SB vs Nehalem.
Reading real world tech articles, when looking at BD vs stars - um...the graphs are very different. When reading about SB vs nehalem they look very similar...

All of those changes were also done in Sandy Bridge! SNB improved prefetching. SNB improved the branch prediction. SNB changed the L2-L3 interface into a ring bus, which was a pretty hefty change on its own. SNB decoupled the decode pipeline from the rest of the execution pipeline, and changed the whole out-of-order part of the machine to accommodate the PRF.

What about SNB and Nehalem look similar to you? The only similarities are in the execution units, and even then they were cleverly reworked to implement AVX efficiently. I think you are unfairly characterizing any differences between Nehalem and SNB as insignificant, while lauding the exact same sort of changes by AMD as the Biggest Changes Ever. That seems irrationally biased to me. It's not based in fact at all.

 

[ElFenix]

can we even be sure that frequency was properly set and displayed?

 

[Khato]

I think you are unfairly characterizing any differences between Nehalem and SNB as insignificant, while lauding the exact same sort of changes by AMD as the Biggest Changes Ever. That seems irrationally biased to me. It's not based in fact at all.

It's typical. Just like the fact that there's rather marked evidence now that integer core frequency in Bulldozer is independent of the rest of the module... but it's a subject that no one else wants to discuss, I'm guessing because they don't want to believe it.

 

[intangir]

It's typical. Just like the fact that there's rather marked evidence now that integer core frequency in Bulldozer is independent of the rest of the module... but it's a subject that no one else wants to discuss, I'm guessing because they don't want to believe it.

Not sure why not. It seems like a cool sort of change to me! Even cooler than the double-pumped ALUs on the P4. Presumably the integer schedulers would be clocked to match. Maybe even the decoders. Actually, come to think of it, it's most probably the FPU that's the odd unit out, in terms of clock. It would make more sense, with the independent FPU scheduling.

 

[SonicIce]

i dont see how the superpi score could be so low because a phenom ii 940 gets the same score
http://www.legitreviews.com/article/860/6/

 

[Khato]

Not sure why not. It seems like a cool sort of change to me! Even cooler than the double-pumped ALUs on the P4. Presumably the integer schedulers would be clocked to match. Maybe even the decoders. Actually, come to think of it, it's most probably the FPU that's the odd unit out, in terms of clock. It would make more sense, with the independent FPU scheduling.

Yeah, it's pretty much a given that the integer schedulers will be on the same clock domain as the rest of integer core. It was actually the same for the Pentium IV. The real question is what the rest of the module is going to be running at... Will it clock up to match the highest integer core? Or will it be a separate max frequency? As the Pentium IV design already proved, there's nothing wrong with having the front end that's feeding the integer core running at a lower frequency. Then the FPU could be at the same or different frequency, and the L2 could be something different too! Once you introduce clock crossings into a high speed design, it makes sense to make the most of 'em, no?

 

[extra]

Don't worry, the old ES samples have absolutely no relevance to how it will actually perform. People have short memories. AMD has made very little actual official performance releases, which is actually a good thing (remember the hyped up phenom disaster). Does no one remember the athlon 64 engineering sample leaks? What were they, from like an 800mhz awful chip or something--then it came out and kicked ass. This thing isn't going to blow sandy bridge out of the water or anything, but get real--it's not going to be slower than an athlon 64x2 in single threaded apps like the engineering sample is. Expect +/- 10-25% diff from similarly priced SB chips depending on how many threads the app can use (not counting FMA or AVX or w/e i have no idea on those).

The question no one has the answer to at the moment (well, that is talking) is how it will overclock. How it performs stock doesn't really matter to me, lol.

 

[Topweasel]

Don't worry, the old ES samples have absolutely no relevance to how it will actually perform. People have short memories. AMD has made very little actual official performance releases, which is actually a good thing (remember the hyped up phenom disaster). Does no one remember the athlon 64 engineering sample leaks? What were they, from like an 800mhz awful chip or something--then it came out and kicked ass. This thing isn't going to blow sandy bridge out of the water or anything, but get real--it's not going to be slower than an athlon 64x2 in single threaded apps like the engineering sample is. Expect +/- 10-25% diff from similarly priced SB chips depending on how many threads the app can use (not counting FMA or AVX or w/e i have no idea on those).

The question no one has the answer to at the moment (well, that is talking) is how it will overclock. How it performs stock doesn't really matter to me, lol.

Yeah the 800 MHz Opteron debacle is still ingrained in my head. Never again.

 

[notty22]

This is a pretty good re-cap of where we are at.
AMD Delays Bulldozer Citing Performance Issues

 

[Arg Clin]

Look at this from a business POV .. if this were any realistic hint of how BD performs, AMD would have abandoned it long ago.

I find it quite safe to conclude that BD will not perform as indicated in this leak. As for the reason/background - it being from a crippled ES chip or even a fake - I have no idea, nor do I find it very relevant as a consumer to be honest.

I'm not saying that BD will necessarily blow SB/IB out of the water - AMD don't really need to in order to reach their core segment. But they will present something competitive at least in the mid range segment - if else, there'd be no business logic behind pressing on. If they were going for low end only (risky strategy, and quite unlikely), they might as well die shrink the K10 - launching a new design indicates that they're aiming higher.

All I'm saying is that this doesn't make sense.