Bulldozer has better IPC when run 4C/4M?

[Kevmanw430]

http://www.xtremesystems.org/forums/showthread.php?275873-AMD-FX-quot-Bulldozer-quot-Review-%284%29-%21exclusive%21-Excuse-for-1-Threaded-Perf.

This was posted before, but the thread got locked because of a misleading title. So, the guy in the link I posted disabled cores 1, 3, 5 and 7 on his FX-8150, and it performed about 20% better in single threaded loads. (Need more benches to confirm, anyone here willing to, if you have an FX?) It makes sense that the cores would perform better when not sharing resources (cache and FPU'), so this is not unexpected. This means, if we can get Win7 or certain programs to schedule in the order 1,3,5,7,2,4,6,8 for the BD cores, it will perform much better in tasks under 4 threads. Think about it. 20% better IPC than PHII and ~4.5GHz in OC, and for 4 threads and under, you'll be a hair behind SB. If you have a program that leverages more than 4 threads, chances are it can also leverage 8, so it won't be too far behind in MT either. Thoughts?

 

[Idontcare]

I get better performance on my 2600K when I disable HT as well. Unless the app is heavily threaded, then I don't.

CMT. SMT. Its the same story as soon as you go away from a CMP architecture.

 

[Kevmanw430]

Which, again, makes perfect sense. But, the fact is, if we can get Windows to schedule threads in the right order, BD might not be such a stinker... Who knows.

 

[ErickMaga]

Which, again, makes perfect sense. But, the fact is, if we can get Windows to schedule threads in the right order, BD might not be such a stinker... Who knows.

I agree on that.

 

[soccerballtux]

http://www.xtremesystems.org/forums/showthread.php?275873-AMD-FX-quot-Bulldozer-quot-Review-%284%29-%21exclusive%21-Excuse-for-1-Threaded-Perf.

This was posted before, but the thread got locked because of a misleading title. So, the guy in the link I posted disabled cores 1, 3, 5 and 7 on his FX-8150, and it performed about 20% better in single threaded loads. (Need more benches to confirm, anyone here willing to, if you have an FX?) It makes sense that the cores would perform better when not sharing resources (cache and FPU'), so this is not unexpected. This means, if we can get Win7 or certain programs to schedule in the order 1,3,5,7,2,4,6,8 for the BD cores, it will perform much better in tasks under 4 threads. Think about it. 20% better IPC than PHII and ~4.5GHz in OC, and for 4 threads and under, you'll be a hair behind SB. If you have a program that leverages more than 4 threads, chances are it can also leverage 8, so it won't be too far behind in MT either. Thoughts?

yes that would be more than acceptable and would be what we wanted from bulldozer.
Please keep us posted with more results! this looks very intersting.

edit: now wait a minute that's showing us benchmarks where it's faster to use the chip in full - enabled mode not half enabled.

 

[Olikan]

I get better performance on my 2600K when I disable HT as well. Unless the app is heavily threaded, then I don't.

CMT. SMT. Its the same story as soon as you go away from a CMP architecture.

yeah...but, 20%?

 

[masteryoda34]

The shared resources (FPU) must have a method of synchronizing access by each core. Some synchronization overhead is bound to occur.

With one core of each module disabled, the cache of each core is effectively doubled.

 

[superccs]

So amd needs to double the cache of each core? It's already a monster...

 

[Vesku]

yeah...but, 20%?

AMD themselves stated a roughly 20% penalty for going CMT over 2 full cores. Problem is that the IPC of one core still seems only Phenom II level IPC. Now odds are IPC will show improvements for tuned software. But why buy the first gen of a new uArch that needs software support. Makes much more sense to see results of second generation and buy if it looks good for your purposes. That's in addition to initial GF 32nm having leakage issues, i.e. these first Llanos and now FX have heat issues starting in the mid 3GHz range.

 

[Kevmanw430]

See, this is the problem. BD just came out, so there is no software optimization, GF is having issues with 32nm, and core scheduling should be 1,3,5,7,2,4,6,8, not 1-8. If all of these things were resolved, BD might actually have a chance..

 

[StrangerGuy]

So, disable 4 cores so the rest of the 4 cores gets their own front-end?

And that defeats the purpose of BD being a 8 core amirite?

 

[Blitzvogel]

So the cores themselves actually catch back up to Phenom II IPC?

 

[Ferzerp]

When it was people saying that this wasn't really 8 cores but was more like 4, they were scoffed at. Now that there is proof, it is interpreted as a good thing?

 

[Blue Shift]

When it was people saying that this wasn't really 8 cores but was more like 4, they were scoffed at. Now that there is proof, it is interpreted as a good thing?

Just stop. We all know how the modules are broken down, and that it depends on how you define cores. The FX-8150 has 8 integer cores. Move on.

 

[Idontcare]

So the cores themselves actually catch back up to Phenom II IPC?

Not the cores, the modules. Disable one Integer core, convert the behemoth 30mm^2 module into a single functioning core (llano core is ~15mm^2 w/cache) and you get IPC parity.

It is rather crazy. Two llano cores w/cache takes almost exactly the same footprint at one bulldozer module.

So instead of having an 8-core llano with no CMT downsides to single-thread throughput, we have an 8-core BD with all the downsides and not of the upsides it would seem.

Phenom has similar issues wrt the athlonX2 at the time though, so I am optimistic that trinity/piledriver will see quite a boost in IPC.

 

[beginner99]

See, this is the problem. BD just came out, so there is no software optimization, GF is having issues with 32nm, and core scheduling should be 1,3,5,7,2,4,6,8, not 1-8. If all of these things were resolved, BD might actually have a chance..

Maybe but this is still AMDs FAIL. Read the review thread where I put links about scheduling. Some people actually saw that the OS scheduler must be aware of the BD architecture for best performance (it knows about HT). So AMD was incompetent to commit MS to make a patch or they thought it was unnecessary. Given the fact, that they have been working on BD for 4-5 Years claiming they did not have enough time would be a bad joke.

 

[crazylocha]

When it was people saying that this wasn't really 8 cores but was more like 4, they were scoffed at. Now that there is proof, it is interpreted as a good thing?

Hence the trashing of BD and JF. Forwarned was the different style of architecture, different meaning to phrase "core". Now everybody starting to figure it out piece at a time.

Timely flashback: dual cores? Why?!? Just make the single core chip oc and you get more calc's per cycle than trying to split tasks up between two cores. Do you realize how much that will bloat the software side having to figure out scheduling, let alone how long it will take just to optimize one? Who the heck wants to program that heavily.

That was just part of an old (very old) conversation under the old copper wires. A little vision goes a looooong way. What conversations will be had in 6 months-2 years from now after a few optimizations?

What were the trashing conversations like when DX11 and Dirt etc first came out?

And here i thought changing the Cobol subs was bad when Quantel came out with a 12 platter interchangable drive (thats 3k per platter for the diaper aged groupies). Bad enough we had to rewrite our own compilers everytime a new chipset came out (i.e. 8088's, Via's, even Timex Sinclairs). Try rewriting for the original Tandy "Color Comp". Those sissies playing with Trash 80's with their cassette players, wait, you mean it RECORDS too??? There goes the neighborhood!! Lol.

35+ years in this mess, and I hate to even open my laptops any more (yes, this is written on my dual core touch screen phone, how Jetsony of me). All this time has taught me patience if nothing else. Maybe some impatient nutter will take some of their precious time and write an optimized Linux version and others will claim it for their own brilliancies in their unique style. Then maybe I will play with it a while, then irratate my wife with yet another hunk of silicone sitting around my other piles of dusty hardware.

Always enjoy the inspiration of forward looking engineers. They push us all to new inspirations. Then we all skew history towards those that we admire when they succeed. What are you going to think when your cell/bank card/car+house key/medical records/ porn player/game machine/cell phone/whateverelsewecomeupwithnext falls in the toilet? Are you going to grab it? Hope that BD/Piledriver dries out well? Maybe it will be SB?!? instead. Who knows. Tomorrow is another day full of new wonders. Maybe you will be the one who tries some new avenue.

Edison and Tesla were both called nuts. AC or DC, both were insane. Gas lights were sooo much safer and easier!!

Ummmm yeah. That worked out well.

 

[BD231]

When it was people saying that this wasn't really 8 cores but was more like 4, they were scoffed at. Now that there is proof, it is interpreted as a good thing?

Thank you. People were saying the FPU's were double the tranistor size of a typical phenom II fpu, which is is entirely false by measure. By slapping two castrated FPU's together they were able to dub it a 256bit part, keyword, TOGETHER.

 

[AtenRa]

Measuring IPC per module is wrong, simple because Bulldozer module has 80% the performance of two cores.

It is like measuring Core i7 2600K with one core + HT instead of measuring two cores without HT.

IPC must be measured in single core, then we measure per module (HT in Intel CPUs) to measure the performance gains of CMT/HT OVER single core.

What OPs results shows is the performance gains from the CMT architecture and not that IPC increases with CMT disabled.

People saying that IPC is lower than Deneb/Thuban are wrong if they measure the 4M/8C Bulldozer to 6C Thuban performance. Measure Single core in both and then draw your IPC conclusion

 

[Vesku]

I've been explaining it AtenRa, but it seems like the "8 cores more like 4 cores" crowd just won't simmer down. It is 8 cores it's just each core is kind of lame and then there is a 20% module hit to each pairs performance.

 

[Dresdenboy]

Thank you. People were saying the FPU's were double the tranistor size of a typical phenom II fpu, which is is entirely false by measure. By slapping two castrated FPU's together they were able to dub it a 256bit part, keyword, TOGETHER.

What you've seen are colored powerpoint boxes. The real silicon looks much different, starting with the 128b FMACs being halved each and the lower half of FMAC#1 sitting next to the lower half of FMAC#2 at one end of the FPU and the other halves at the other end...

 

[Dresdenboy]

I've been explaining it AtenRa, but it seems like the "8 cores more like 4 cores" crowd just won't simmer down. It is 8 cores it's just each core is kind of lame and then there is a 20% module hit to each pairs performance.

And then there is inefficiently decodable code blocking important shared front end resources.

 

[Vesku]

Yeah some strange scenarios where the cores can't be fed properly going on in certain tests.

 

[zlejedi]

So have anyone actually run strictly 4 threaded code on 8 core BD with 4M/8C and 4M/4C scenario ?

Because 4M/4C being faster than 2M/4C is discovery worthy of captain obvious award.

If 4M/4C would be faster than 4M/8C in any scenario then it would prove that indeed there's some kind of problem with scheduling.

 

[dawp]

So what are the chances of AMD releasing an optimizer like they did with the dual core when they first came out?