Bulldozer prices leaked

[AtenRa]

Since Intel has the manufacturing advantage, it is unlikely that BD will be able to overclock beyond 4.7ghz-4.8ghz that SB can already do now.

I believe you know that BD will be manufactured at 32nm and even if we don’t know GloFo’s 32nm process specs, I will guess they are at least at the same level as Intel’s 32nm because they use both SOI and HKMG when Intel only use HKMG. So theoretical if someone has the advantage in 32nm that is AMD and not Intel.

 

[Idontcare]

I believe you know that BD will be manufactured at 32nm and even if we don’t know GloFo’s 32nm process specs, I will guess they are at least at the same level as Intel’s 32nm because they use both SOI and HKMG when Intel only use HKMG. So theoretical if someone has the advantage in 32nm that is AMD and not Intel.

If we were to make educated guesses as to how the relative advantages stack up then we'd be inclined to give Intel the advantage here.

SOI reduces power-consumption whereas gate-last HKMG integration yields higher drive-current transistors.

(GloFo's gate-first HKMG will inherently have lower drive currents compared to Intel's on a voltage-normalized basis, a key metric of xtor performance assessment in the industry that we should not simply ignore for the sake of conversational expediency)

But to be sure it is a toss-up as both approaches offer the CPU design and layout engineers different avenues to maximizing the performance of the end-product IC. As is evidenced by the performance of AMD's 45nm-based products in comparison to Intel's 45nm-based products.

The problem for AMD though will continue to be the same, they may well field competitive parts on a process-node normalized basis but they are a day late which translates them into being a dollar short.

GloFo's 32nm could give Intel's 32nm a run for its money but it will still be a rather short run because Intel's 22nm is right around the corner now The cycle is unbreakable given the revenue disparity and R&D disparity between the two.

 

[Arachnotronic]

Idontcare, I just want to point out -- sorry if this is a derailment -- that I really enjoy reading your posts. It seems like you really know what you're talking about...it's really nice

 

[RussianSensation]

uhhh whutttt?????
The module design is set on 90% throughput per core when each of the cores is fully loaded. Most of the time, due to the software, the throughput loss won't be noticable compared to two seperate cores at all.

That's contradictory to AMD's own slides. You can read up the link which I posted earlier in this thread. They stated 80% efficiency. So suddenly you think that 20% is irrelevant? Remember they are comparing full-fledged dual cores. So it's relative to each type of a design.

Also the ipc is higher on BD. We just don't know how much.

I never stated that I know what the IPC for BD is. I did try to make what I thought was a reasonable mathematical estimate based on the current advantage in IPC that Nehalem and SB have over Phenom II.

Then again you talk about the FX-4, the FX-8 does not suffer that possible throughput loss on 4 loaded cores.

Why is AMD pitting a 6-core BD vs. a 4-core 2500k? If a 4-core was fast enough to beat a 4-core Sandy Bridge, they'd position the 6-core at 2600k level and price 8-core BD at $500 to improve their profitability.

SB frequency ceiling is not the limit, it is the limit for SB!!! SB ipc is not the ceiling, it is the ceiling of SB.

I never said it's the utmost ceiling from all processors in the world. I was comparing SB strictly to current x86 processors, which we consumers buy for PC building. In this case out of Nehalem, Lynnfield, Phenom II, SB has the highest IPC and the highest clock frequency ceiling (and the best power consumption too). Its primary weakness is that while their highest 2600k offering supports 8 threads, that's only possible as a result of HT. So a more optimized 8 threaded processor could beat it in multi-threaded tasks like rendering (i.e., Cinebench).

IPC only becomes important when they both hit the same frequencies, which you just assume without any proof whatsover

When the last time AMD processors overclocked to higher frequencies than Intel processors? As far back as Pentium 3, Intel always had a frequency advantage or was at least on equal footing. So it's highly unlikely that Sandy Bridge will suddenly have a 5.5-6.0ghz overclocking ceiling. This implies that shipping parts will come in at a more reasonable 3.8-4.0ghz clock speeds which isn't far from Sandy Bridge. In fact, Intel cites its main competitive advantage as its advanced manufacturing. Because Intel is always a step ahead of AMD in node design that it makes it so much more difficult for AMD to compete head-on. This is why the Athlon 64 was such an innovative processor - AMD knew they couldn't beat Intel on frequency, so they had to go with efficiency.

Also, you talk about Pentium 4 having a higher frequency ceiling if it was manufactured on 32nm process. That's comparing apples and oranges since Pentium 4's NetBurst architecture was made specifically to achieve high frequencies. When you try to create a processor with efficiency/IPC in mind, the way the pipeline is designed makes it harder to clock to such high frequencies. So if anything, the more complex BD becomes in trying to maximize the IPC, the harder it will be for it to scale to even higher frequencies.

Both metrics are important in the performance of a cpu. both metrics are determined by the indivual cpu and not the competition.

Competition certainly raises the bar for how much of an improvement in IPC / clock / watt is necessary. Phenom architecture is a perfect example of AMD resting on their previous successes with Athlon 64 architecture. This time they know exactly how fast Sandy Bridge is. The redesign will help them improve IPC significantly from Phenom II but I don't think it will be enough to beat Sandy Bridge. Based on the enormous performance in IPC that Sandy Bridge currently enjoys over Phenom II, AMD has no choice but to increase frequency and throw in more cores. And this is exactly what rumours point to - higher clockspeeds than Phenom II and even more cores (the more cores is confirmed of course ).

GloFo's 32nm could give Intel's 32nm a run for its money but it will still be a rather short run because Intel's 22nm is right around the corner now The cycle is unbreakable given the revenue disparity and R&D disparity between the two.

Thanks for that explanation IDC!! It appears that Intel will postpone the launch of Ivy Bridge until Q2 2012. This gives AMD a reasonable window to make an impression.

 

[Tuna-Fish]

When the last time AMD processors overclocked to higher frequencies than Intel processors? As far back as Pentium 3, Intel always had a frequency advantage or was at least on equal footing. So it's highly unlikely that Sandy Bridge will suddenly have a 5.5-6.0ghz overclocking ceiling. This implies that shipping parts will come in at a more reasonable 3.8-4.0ghz clock speeds which isn't far from Sandy Bridge. In fact, Intel cites its main competitive advantage as its advanced manufacturing. Because Intel is always a step ahead of AMD in node design that it makes it so much more difficult for AMD to compete head-on. This is why the Athlon 64 was such an innovative processor - AMD knew they couldn't beat Intel on frequency, so they had to go with efficiency.

AMD processors have had lower clockspeeds for the past ~10 years because they were designed for low speeds and high efficiency (= long critical paths in the processor). The leaks and information we have on BD tells us it's the other way around this time -- BD has much shorter critical paths in the processor, and thus much higher clock ceiling. This has been discussed at length in this thread This thread.

 

[AtenRa]

If we were to make educated guesses as to how the relative advantages stack up then we'd be inclined to give Intel the advantage here.

SOI reduces power-consumption whereas gate-last HKMG integration yields higher drive-current transistors.

(GloFo's gate-first HKMG will inherently have lower drive currents compared to Intel's on a voltage-normalized basis, a key metric of xtor performance assessment in the industry that we should not simply ignore for the sake of conversational expediency)

I will have to disagree here,

SOI will not only lower the leakage but it will raise the performance of the xtor.

http://www.soiconsortium.org/pdf/SOI_Implementation_WhitePaper_Infotech_v2.pdf

1.1 SOI Basics

The insulating layer increases device performance by reducing junction capacitance
as the junction is isolated from bulk silicon. The decrease in junction capacitance also
reduces overall power consumption.

1.2 SOI Floating Body

In Silicon-On-Insulator process technology, the source, body, and drain regions of
transistors are insulated from the substrate. The body of each transistor is typically
left unconnected and that results in floating body. The floating body can get freely
charged/discharged due to the transients (Switching) and this condition affects
threshold voltage (Vt) and many other device characteristics.

The The transistor area in SOI process is less because there is no need for metal contacts
to Wells used for making MOS transistors.

1.4 Partially Depleted SOI

Charging of the transistor body (floating body) leads to a change in the threshold voltage, if this is properly taken into account in the IC conception then the
result is a faster switching, thus higher performance at same Vdd!

1.5 History Effect

1.6 Stack Height Effect

Due to floating body in PD and low substrate effect in FD, in a stack of transistors,
the Vt of the upper device results smaller than in bulk, improving performances.
Then the first switch is typically 20-30 % faster than in bulk, while the second switch
is even faster.

Gate first will give them higher density and lower manufacturing cost at an expense of lower drive current but they will gain that with the SOI, plus they will be able to use more Voltage in order to have lower Gate delay (if they will want it) and at the same time have lower power usage.

All that is theoretical because we don’t have the hard numbers from both process in order to compare them but i will have to say that AMD at the same nm process with HKMG and SOI has the theoretical advantage.

Since the two micro architectures (BD vs SB) are not the same nor are the manufacturing processes, we have no clue how high in frequency the BD will be able to operate and since a lot of experts have said that BDs design was made with higher frequencies in mind i will have to say that without having the real McCoy in our hands statements like "Since Intel has the manufacturing advantage" and "BD will not be able to OC beyond 4.7-4.8GHz" lack any real hard data.

 

[jimbo75]

Phenom currently uses CMP, or chip-level multiprocessing (i.e. just cramming multiple cores on a single chip). A single Bulldozer module (i.e., 2 cores) would only have 80% of the performance of 2 fully fledged cores in CMP design, all things being equal. What this means is that without any other changes a 6-Core Bulldozer CPU is only 80% as fast as a 6-core Phenom II. This means AMD will have to compensate significantly with clock speed, IPC improvements and well more cores (hence the 8-core BD spec at $320).

I am just afraid some are misinterpreting this the opposite way -- i.e., "Bulldozer is like an 6-Core Phenom but even more efficient". In fact, what AMD slides are showing is the opposite: "If a 6-Core BD was 25% more efficient than Phenom II X6 per clock, it would only be as fast as an Phenom II X6 at the same clock speed."

What this would mean then is if the 80% efficiency is taken at face value from AMD's internal slides, then for BD to match Nehalem, it would need to be a whopping 75% more efficient per clock cycle than a Phenom II was (i.e., we need to go from 80% to 100% to match Phenom II and then another 40% to get to Nehalem over Phenom II --> 0.8 --> 1.4x or a 75% increase).

Except it isn't 25% slower than phenom II out of the gate.

The 180% figure is based on two separate bulldozer cores vs a bulldozer module

http://blogs.amd.com/work/2010/08/30/bulldozer-20-questions-–-part-2/

Compared to CMP (chip multiprocessing – which is, in simplistic terms building a multicore chip with each core having its own dedicated resources) two integer cores in a Bulldozer module would deliver roughly 80% of the throughput.

 

[RussianSensation]

Except it isn't 25% slower than phenom II out of the gate.

The 180% figure is based on two separate bulldozer cores vs a bulldozer module

http://blogs.amd.com/work/2010/08/30/bulldozer-20-questions-–-part-2/

I said specifically if you were to take a Phenom II X4 and convert that CMP design into a Bulldozer "style" Module, at the same clock speed and identical performance per clock, you will get 25% slower performance out of the gate. I should have clarified Integer Performance as you pointed out. Then I said this is your starting point, and everything extra from here on out are:

1) Additional cores
2) Additional improvements in IPC
3) Additional improvements in frequency.

But my point was you are starting at 80% of Phenom IIs performance out of the gate since you moved away from CMP design. This means to get to get to 1.4x the performance per 2 cores (not per clock) from Phenom II (i.e., to get near Nahelam/Lynnfield) in performance, you need to go from 0.8x to 1.4x or a 75% performance increase (which will have to come from #2 and #3 points above). That's a tremendous mountain to climb...which is why AMD has no choice but also revert to #1 to compete.

....and now it appears Bulldozer may be a paper launch.

 

[piesquared]

What launch? I don't recall AMD ever giving a launch date. As far as Bulldozer in September, AMD has repeatedly said that servers will launch late summer so nothing has changed.

 

[RussianSensation]

What launch? I don't recall AMD ever giving a launch date. As far as Bulldozer in September, AMD has repeatedly said that servers will launch late summer so nothing has changed.

The launch was supposed to happen in June/July. It doesn't really matter if AMD announced the date at this point. If they are delaying their "unofficial" launch until the Fall, they'll not only have to compete with lower priced Gen 1 Lynnfield processors, but also S1155 and LGA2011. Poor execution on AMD's part if this is true. And also signals that they may have manufacturing yield problems, specifically reaching those high clock speeds necessary to be competitive while achieving reasonable yields.

If you look at Intel's latest roadmap, not only did they delay Ivy Bridge, but Core i5 2500k and 2600k will continue to remain the key processors in each of their target segments until Q1 2012. This means Intel doesnt' expect BD to change the performance landscape.

statements like "Since Intel has the manufacturing advantage" and "BD will not be able to OC beyond 4.7-4.8GHz" lack any real hard data.

It is pretty much common knowledge that Intel has the manufacturing advantage over AMD. They are always 1 step ahead. When BD shifts to 32nm, Intel will only be 6 months away from 22nm design. By this time, their 32nm manufacturing will have matured and they'll be able to deliver even more cores processors without increasing the power envelope too much (6C SB-E) or will be able to increase frequencies on current 4C SB processors without affecting the TDP (higher binned 2500/2600k processors). It is one of firm's key competitive advantages. It's something that's talked about all the time. There is even a term they coined: "Intel Manufacturing Advantage".

It is true that we don't have any real world data to dispute for certain that BD won't clock beyond 4.7-4.8ghz, but given the additional complexity and AMD's track record, they haven't had the better overclocking processor compared to Intel in the last 5 years. So the odds are stacked against them for having BD overclock to 5.5-6.0ghz. And with current rumors that BD may be delayed into September, it doesn't even look like they are able reach current targeted base clock speeds with given yields.

 

[drizek]

Or maybe the reason why AMD delayed Bulldozer is because the i5 2500K is doing so poorly against Phenom II...

 

[piesquared]

ivy bridge will compete against Witchita, Krishna, Trinity, Komodo, Terramar and Sepang. And only Krishna and Witchita(and Llano, since sandy bridge still doesn't have DX11 or OpenCL on GPU) initialy, as intel plans to releasee the low end first according to their roadmap. sandy bridge will compete with Llano (minus DX11 and OpenCL). sandy bridge e against Bulldozer and everything looks to remain on track. advantage AMD

 

[OCGuy]

Or maybe the reason why AMD delayed Bulldozer is because the i5 2500K is doing so poorly against Phenom II...

...

???

 

[podspi]

The problem for AMD though will continue to be the same, they may well field competitive parts on a process-node normalized basis but they are a day late which translates them into being a dollar short.

GloFo's 32nm could give Intel's 32nm a run for its money but it will still be a rather short run because Intel's 22nm is right around the corner now The cycle is unbreakable given the revenue disparity and R&D disparity between the two.

BD should have about 6 months to compete w/ Intel @ 32nm -- longer since IB will be hitting lower/mid-end first.

...

???

I believe it was a joke. Some people's first reaction to IB's alleged delay was that Intel intentionally delayed IB because BD was going to suck. So clearly, if BD is delayed, it is clearly because PhII is bringing the pain

 

[jimbo75]

I said specifically if you were to take a Phenom II X4 and convert that CMP design into a Bulldozer "style" Module, at the same clock speed and identical performance per clock, you will get 25% slower performance out of the gate.

Where did you say that specifically?

I should have clarified Integer Performance as you pointed out.

I didn't point out anything about integer performance.

But my point was you are starting at 80% of Phenom IIs performance out of the gate since you moved away from CMP design.

Bullshit, you mention over and over that BD has to overcome a 25% reduction vs Phenom II just to get equal on numerous occasions. Your entire argument was based on a house of cards on a shaky foundation.

 

[alexruiz]

...When BD shifts to 32nm, Intel will only be 6 months away from 22nm design.

Shift? BD is launching on 32nm. There is no shift

 

[alexruiz]

I am curious as to why the role of GF is being downplayed. Fab 30 (or 35?) in Dresden has always been one of the most advanced in the world. When AMD spun off the manufacturing side, the intention was to have 2 entities clearly focused on different yet complementary stuff. GF also got very healthy infusion of cash form Dubai, and money helps

 

[RussianSensation]

Where did you say that specifically?

I didn't point out anything about integer performance.
Bullshit, you mention over and over that BD has to overcome a 25% reduction vs Phenom II just to get equal on numerous occasions. Your entire argument was based on a house of cards on a shaky foundation.

Huh? Read my posts again. I'll try to explain another way:

CMP Phenom II 2 core design = 100% performance at X clock speed.
Module Phenom II style 2 core design = 80% performance at X clock speed.

Now "turn" that Phenom II into the new Bulldozer design --> which means adding higher IPC (variable y), higher frequency (variable z).

Therefore, your Bulldozer 2-core architecture would be 0.8X * (1+y) * (1+z) faster than 2 Phenom II cores, which is 1.0X. So for instance, if Bulldozer's IPC improves 25% (variable y) and frequency is the same (same clock speed), we will be at 0.8X * (1.25) = 1.0X only = Phenom II.

In simple terms, if 2 core "Bulldozer architecture" is 25% more efficient per clock cycle, at the same clock speed it will only match a stock Phenom II 2 core design because out of the gate the Module design is only 80% as efficient as the CMP design. This is exactly what I said earlier.

If you don't agree with this, please explain but otherwise reread the architecture article provided by TechReport. It's all stated there. I am not "BSing" anything.

Also, in post #132 you quoted the 80% stat related to two integer cores. So you did allude to integer performance.

Shift? BD is launching on 32nm. There is no shift

I know. Thanks for correcting that part. I meant when AMD launches their new architecture on 32nm, Intel will be at 22nm in only 6 months.

 

[podspi]

RussianSensation, your logic is missing one critical point: Everything you say only applies to the case where there are two threads on a module (presumably at a utilization of 100%).


When there is one thread on a module this performance degradation does not occur. Not only that, but this resource sharing allows higher clocks to be achieved, so for bursty singlethread workloads singlethread performance should equal or higher in a hypothetical CMT Phenom II.

Now, for multithreaded workloads, the FX8xxx series already has 33% more cores than the X6, so your 25% is already made up

The really interesting question is when we have something like a game that uses 4-threads heavily. In this case, a hypothetical Phenom II built with CMT may end up with equal performance, or might not (again thanks to higher clockspeeds and turbo). We'll see soon enough, hopefully.


I would expect that vs a hypothetical single-core BD and a single-core Deneb, the BD should be much faster, even at the same clock speed. That should make the difference even easier to make up in situations where CMT is not as advantageous.

 

[Dekasa]

I may have missed the beginning of Russian's thing, or I may be reading it wrong, but AMD stated their module design scaled 2 cores to 180% of one core, so shouldn't Bullldozer only have to be ~11% faster to reach an equal Deneb (1 module vs. 2 cores). It's not two 80% cores, it's two 90% cores.

 

[Soleron]

I may have missed the beginning of Russian's thing, or I may be reading it wrong, but AMD stated their module design scaled 2 cores to 180% of one core, so shouldn't Bullldozer only have to be ~11% faster to reach an equal Deneb (1 module vs. 2 cores). It's not two 80% cores, it's two 90% cores.

The 80% claim was compared to a single thread per module. It does not relate the IPC of previous cores to BD; BD could be faster or slower at the same core count and clockspeed.

It's analogous to Intel's ~20% speedup going from one core to one core with HT.

But you are right. If Russian's logic makes any sense (and I don't think it does), he should use 90% rather than 80%. He's still trying to compared IPC between generations for which there is no basis yet.

Russian, you're also missing the two extra cores AMD can add to the BD die because of the space saved by using modules. Your hypothetical no-module BD would be six cores.

 

[RussianSensation]

He's still trying to compared IPC between generations for which there is no basis yet.

I never said BD will have similar IPC to Phenom II. My sole purpose was to highlight just how far ahead SB is of Phenom II. Therefore, BD has a mountain to climb. That's all there is to it.

Russian, you're also missing the two extra cores AMD can add to the BD die because of the space saved by using modules. Your hypothetical no-module BD would be six cores.

Oh I know BD will have more cores. I was only talking about single threaded performance though on a per core basis. If you followed my logic, I believe that BD will NOT match SB in IPC. Therefore, AMD will add more cores and higher frequency to compete.

RussianSensation, your logic is missing one critical point: Everything you say only applies to the case where there are two threads on a module (presumably at a utilization of 100&#37.

Right, but keep in mind SB is still about 50% faster in IPC than Phenom II is. So even comparing 1 core to 1 core, even if we discount the 80% "penalty" for 1 core, BD still needs to come up with 40-50% more performance PER core than Phenom II does to match SB at the same clock speed. My feeling is AMD will ship a 4.0ghz processor to compete with the 3.4ghz 2600k.

 

[Nemesis 1]

So they intend to compete with SB i7, better have the performance to stay competitive at that price.

Well actually they are pricing to compete with socket 1155 i7 is designation of HT on 2600. They are not pricing to compete with SB-E socket 2011

 

[Abwx]

Right, but keep in mind SB is still about 50% faster in IPC than Phenom II is.
.

Although SB has a big IPC advantage, i dont see it being as high
as the erratic number you re quoting..

You are just spreading wrong numbers as a mean to support your
random perfs comparisons.

http://techreport.com/articles.x/20486/12

 

[Nemesis 1]

You AMD guys really are a treat . Your comparring a 4 core to a 6 core. If anything a six core SB will be over 70% faster than the 6 core amd your comparing to. The 6 core intel in your link is a little over 40% faster . Whats up with you guys? Apple to apple . Russian was talking IPC . so you compare 4 cores to six cores and you think you debunked russian . Na you just made yourself look the fool.

Actually if you look at the highest end AMD 4 core in your link it is more than 50% slower. SB-E will be even faster . NOW laydown rollover and play dead.