Cache/uncore speed performance in 4770k

[ali1988]

Just wondering if anyone has tested the performance impact of increasing cache/uncore speed above stock when overclocking. E.g. If a 4770k is overclocked to 4.3ghz, is it worth raising the cache speed to ~4.3ghz. And if so, how much performance gain is there actually (e.g. in single threaded super pi or a multi threaded benchmark program) and what impact if any does this have on min stable vcore.

I'm assuming no difference to vcore as theres a seperate uncore/cache voltage?

 

[JimmiG]

Very small impact on performance. No reason not to run the uncore as high as you can, but it's not worth the effort to really push it to the limit.

 

[BonzaiDuck]

Just wondering if anyone has tested the performance impact of increasing cache/uncore speed above stock when overclocking. E.g. If a 4770k is overclocked to 4.3ghz, is it worth raising the cache speed to ~4.3ghz. And if so, how much performance gain is there actually (e.g. in single threaded super pi or a multi threaded benchmark program) and what impact if any does this have on min stable vcore.

I'm assuming no difference to vcore as theres a seperate uncore/cache voltage?

I'm assuming what I heard (read here) is what I would otherwise assume: there is no way to increase L1 and L2 cache speeds. The "skinny" is that your Z87 mobo (I'm assuming . . ) allows you to tweak the L3 cache. But tweaking the L3 cache doesn't matter much. It is the cache size -- buffering between RAM and the L2 cache -- which provides the performance advantage. Tweaking the cache speed won't amount to much of an improvement.

 

[Lepton87]

Doesn't the L3 cache run at core speed since SB? I remember that in Nehalem it run at 2GHz but increasing its speed had little impact on performance.

 

[mindbomb]

should improve the performance benefit of hyperthreading

 

[sefsefsefsef]

Doesn't the L3 cache run at core speed since SB? I remember that in Nehalem it run at 2GHz but increasing its speed had little impact on performance.

Sandy Bridge had the L3 cache frequency be equal to core frequency, but Ivy Bridge went back to core frequency/2 for the L3 cache. As far as I know, Haswell also has core frequency/2, and I assume they will continue to use that going forward.

There are very small performance reasons for running the L3 cache faster, but there could be larger power reasons to run it at half frequency. Obviously on the desktop using a 4770K you wouldn't care about power consumption, but when Intel is trying to squeeze Haswell and future chips into smaller and smaller TDPs, cutting the L3 frequency is an obvious place to save power.

 

[Lepton87]

Sandy Bridge had the L3 cache frequency be equal to core frequency, but Ivy Bridge went back to core frequency/2 for the L3 cache. As far as I know, Haswell also has core frequency/2, and I assume they will continue to use that going forward.

There are very small performance reasons for running the L3 cache faster, but there could be larger power reasons to run it at half frequency. Obviously on the desktop using a 4770K you wouldn't care about power consumption, but when Intel is trying to squeeze Haswell and future chips into smaller and smaller TDPs, cutting the L3 frequency is an obvious place to save power.

Thanks, that explains a lot. I didn't realize that they went back to separate L3 cache frequency with IB.

 

[Racan]

Thanks, that explains a lot. I didn't realize that they went back to separate L3 cache frequency with IB.

That's because they didn't do it with IB, Haswell brought back the decoupled L3 cache


http://www.anandtech.com/show/6355/intels-haswell-architecture/10

 

[sefsefsefsef]

That's because they didn't do it with IB, Haswell brought back the decoupled L3 cache


http://www.anandtech.com/show/6355/intels-haswell-architecture/10

I'm having trouble finding a source for my claim, although I'm pretty sure it's true. Sorry. I did find this article, though:

http://www.hardwareluxx.com/index.p...-core-i7-3770k-and-all-i5-models.html?start=5

The text of the article says that there is no difference between the cache bandwidth of SB and IVB, but I believe the graphs which they show tell a different story (SB has more per-clock cache bandwidth than IVB). Believe whatever you want.

I will finally say that there's a lot more going on in IVB's L3 cache than you will find in an Anandtech article, such as this:

http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/

 

[bronxzv]

As far as I know, Haswell also has core frequency/2

my understanding is that the L3 cache can run at core frequency or a bit less / a bit more since it has a separate ratio setting, definitely not only at half core frequency

for example on my ASUS mobo with the AI Suite III utility Under the CPU Frequency tab I can change these:

BCLK Frequency (default 100 MHz)
Ratio (for example 39, for turbo core frequency at 3.9 GHz)
CPU Cache Ratio (for example 39 for L3 cache frequency at 3.9 GHz)

[EDIT] it is explained here http://www.realworldtech.com/haswell-cpu/6/ at the 3rd paragraph "Second, the ring and LLC are on a separate frequency domain from the CPU cores."

 

[JoeRambo]

The text of the article says that there is no difference between the cache bandwidth of SB and IVB, but I believe the graphs which they show tell a different story (SB has more per-clock cache bandwidth than IVB). Believe whatever you want.

SB and IVB is pretty much the same core and L3 cache architecture is the same. Only minor details got tuned.

HSW decoupled "uncore" and gave it different clock domain, so they can have flexible situations, like IA cores on 800Mhz and iGPU on max clock and 100% load requiring massive bandwidth from L3.

 

[Homeles]

Very small impact on performance. No reason not to run the uncore as high as you can, but it's not worth the effort to really push it to the limit.

Beauty is in the eye of the beholder. There's not a point to taking these things under liquid nitrogen, but people do it anyway.

There aren't really a whole slew of benchmarks out there regarding the subject. You'd think there would be.

Sandy Bridge had the L3 cache frequency be equal to core frequency, but Ivy Bridge went back to core frequency/2 for the L3 cache. As far as I know, Haswell also has core frequency/2, and I assume they will continue to use that going forward.

There are very small performance reasons for running the L3 cache faster, but there could be larger power reasons to run it at half frequency. Obviously on the desktop using a 4770K you wouldn't care about power consumption, but when Intel is trying to squeeze Haswell and future chips into smaller and smaller TDPs, cutting the L3 frequency is an obvious place to save power.

As far as I know, the only notable changes with Ivy's L3 was that it is dynamically resizeable, and there was a dedicated L3 added to the GPU to prevent waking unnecessary resources.

 

[ali1988]

Awesome, thanks for the info. To clarify though (and I hate to ask this here instead of justtrying it myself but unfortunately don't have a 4770k handy atm), seeing as they're uncoupled would it therefore true that raising cache frequency would not require any bumps in vcore to retain stability? E.g. if minimum stable voltage for 4.3ghz is exactly 1.243v with cache frequency 3.9Ghz, would raising it to 4.2 or 4.3ghz require vcore bump for the entire chip to retain stability?

Reason I ask is I figure I may as well increase it a bit if there's no additional vcore requirement, a possible slight speed boost and no downside.

 

[JoeRambo]

A thought experiment: if rising uncore speed increases performance, that means more instructions got processed faster, because core overall memory subsystem was faster (= more core heat, tighter tolerances required). Beyond that, uncore is competing for thermals, power supply and creating additional instabilities that way.

So overall, stability testing is your best friend

 

[ali1988]

Yeah makes sense as they're all on same die. I guess i figured it was a bit like raising the memory speed from 1600 to 1866, sure there's slightly extra load on the imc but its small enough that it doesn't require voltage bump for either vtt or (presumably) vcore at any given moderate OC. Now that I think about it though this is still an assumption, I've never tested minimum vcore before and after adjusting mem speeds...