can anyone explain the DDR ram settings?

[TuffGuy]

or have a link to a page that explains what they do and how important they are? i'm currently running at 160mhz fsb and 8-8-6-2-2-2-2, but i'd like to know what i'm sacrificing for speed.

 

[jonnyGURU]

Wow! And it's stable?

I can't push 140 MHz without changing my CAS latency to 2.5 and I've got 6 layer PCB Samsung DDR CAS2 PC2100!

Even modules from Crucial and Mushkin don't have > 266 DDR that does CAS2 (well, the Mushkin "High Performance" PC2100 CAS2 that they are only taking Pre-Orders on ran at 147 on an Iwill KA266, but....).

I'm impressed.

 

[jonnyGURU]

Oh.... and to answer your initial question. Personally, I don't know what all of the numbers mean. The last three are the ones that you always see, though.

CAS (Column Access Strobe) Latency (controls the latency between the SDRAM read command and the time that the data actaully beomes available), RAS Precharge Time (RAS meaning Row Access Strobe, this controls the idle clocks after issuing a precharge command to the SDRAM) and RAS to CAS Delay (this controls the latency between the SDRAM active command and the READ/WRITE command).

I'll look in my BIOS to see what the other settings are.

 

[jonnyGURU]

Me again....

Even though I have a Biostar M7MIA and these guys used a K7M Master, they have the same settings. They don't explain what BH Limit, Idle Limit, etc. MEAN or DO, but they do share what gave them the best performance. Check it out.

 

[Pabster]

I'm running 2 newer sticks of Crucial PC2100 @ 166 8-8-6-2-2-2-2, rock stable without a hitch. Pretty impressive for $46/stick stuff

 

[WildeBeast]

Same here PAbster. I bought one strick for $56 about two weeks ago, PC2100 CL2.5 that runs fine up to 158 at 8882222 (although I hear that 8882622 is better) at standard voltage (2.5) I never bother with CL2.5, it doesn't let me get any higher, and I dont bother to run the system oast 158 anyway. The stuff will hit 165 at 2.7 though, that is the highest I went because other parts dont like speeds that high, specifically my VC. pumping AGP doens't help either. BTW I am using the GA-7DXR.

 

[Insane3D]

I run my DDR @ 2.9v and it doesn't even get warm. I have also found that 8882622 to be less stable. Here's some good info regarding the Epox DDR settings:

"SDRAM Page Hit Limit
Because under normal operation conditions, there is only a limited probability that the next read command will hit the same page as the previous one, chances for a page miss increase exponentially after each consecutive page hit. In case, the page is still open, this means that it needs to be closed first before another row select command can be issued. Therefore, it is better to force a page closing after a certain number of page hits. This will shave off the number of latency cycles required for a Precharge (tPR) from the overall page miss latencies. For gaming applications with a high locality of data, the best performance will be achieved by setting this entry to the maximum value of 16, which will further increase stability.

SDRAM Idle Limit

This setting relates to the Page Hit Limit. Because there is not only a spatial constraint on how many consecutive hits can go to the same page but, moreover, a temporal component as well, the controller can be programmed to close a page if there have been no read requests in a given number of bus cycles. Recommended setting: 8 cycles

SDRAM tRC Timing Value

The minimum time between two consecutive accesses of the same bank. Parameters needed to be taken into account are tRCD and CAS latency as well as Precharge (tRP) (see below). As a rule of thumb, tRC should be set such that it is the sum of tRAS and tRP.

SDRAM tRP Timing Value

When a bank is open and a page miss occurs, the bank needs to be closed before the next bank activate command can be issued. Electrically, this is done by resetting the RAS lines to neurtral by means of a precharge that erases all information accumulated as function of the last bank activate command. In most cases, 2 cycles are enough, for higher speed, 3 cycles are recommended.

SDRAM tRAS

tRAS is the RAS pulse width, that is the time required for the bit-lines to build up the voltage potential necessary for restoring the data to the memory cells of origin. Setting tRAS too short will eventually cause data corruption not only in the memory array but can also cause hard drive corruption. Historically, tRAS was defined as the sum of tRCD and CAS latency, however, with the current high speed DRAMs, this equation no longer holds. As a rule of thumb, at 100 MHz memory bus speed (200 MHz data rate) a tRAS of 5 cycles suffices in most cases. At or above 133 MHz using tRAS of less than 6 is like playing Russian Roulette. tRAS has little or no impact on performance unless software is used that causes totally random accesses.

SDRAM tRCD and CAS latency

CAS latency is the most important parameter for system performance, RAS-TO-CAS Delay is secondary but the parameter hardest to keep short in current DRAM designs."

I found this here.

 

[TuffGuy]

thanks for the info guys.

and yes, i'm also using crucial pc2100. $50 with shipping and taxes just cannot be beat.