32 cores* at a likely base frequency of 2.8-3.0 GHz vs. 22 cores* at a base frequency of 2.4 GHz!
*with each core roughly comparable in IPC.
1. Thread parent in the same paragraph claimed that Zen would be a hit in HPC while simultaneously denying the existence of AVX software. HPC runs 100% AVX workloads, and HPC-specific literature talks about AVX throughput extensively.
The paper Early performance evaluation of AVX for HPC shows AVX producing a performance benefit of more than 10% on 3 of the 15 benchmarks. Things many have changed since 2011, but if not it would seem that Zen could perform well on many HPC workloads.
We utilized preproduction system with the first member of AVX enabled CPU, the new 2nd generation Intel Core I7-2600 processor. We have found that evaluated platform shows significant performance improvement versus exactly the same configured platform but without AVX support. The performance improvement we have been able to observe behaves as we have been expecting taking in to account theoretical performance of both CPUs. Intel AVX delivers significant performance improvements to compute-intensive codes and for same test we have observed 88% difference between AVX version and SSE 4.2 version. The impact is significantly smaller when the application is memory-bound as both platforms have the same configured memory subsystem. As might be expected, for larger systems the interconnect bandwidth and topology have an increasing impact but in our testing scenario limited to the single platform all such tests, do not show any advantage or disadvantage for AVX platform as in fact they are irrelevant for a single socket platform validation. The performance advantage of compute-intensive benchmarks on AVX enabled platform is between 1.58 and 1.88 over the version limited to SSE 4.2. All not compute-intensive benchmarks show around 8% to 10% performance improvement. Intel Turbo Boost Technology was always enabled and delivers additional frequency improvement and consequently improvement in performance.
* * *
In summary, we can state that AVX even in the early phase of the platform implementation not optimized for HPC brings lot of performance improvement for compute intensive applications and become a compelling choice for many of the new HPC installations.
I see a lot of misconceptions in this thread.
1. Thread parent in the same paragraph claimed that Zen would be a hit in HPC while simultaneously denying the existence of AVX software. HPC runs 100% AVX workloads, and HPC-specific literature talks about AVX throughput extensively.
Zen is clearly an efficient design, and it could potentially replace Intel or act as a second vendor in a range of server use cases, particularly web and database. However, there are several obstacles preventing it from being a general replacement for Intel's Xeon series. Lack of AVX (especially AVX-512) units make it entirely irrelevant in HPC. Current rumors for Naples indicate a 4-die MCM package, which would essentially be three layers of NUMA (2 sockets, 4 dies, 2 CCX per die). Compared to Intel's unified L3 cache on Xeon E5s, this would be a significant challenge to scale-up (big server) workloads.
That's a bit of a misrepresentation:
Basically, things that AVX should improve, improved a lot. Things it shouldn't improve, didn't get significantly worse.
I don't see how you could conclude his post was saying AVX made things worse. I think both his post and the data from the article support the idea that AVX offers tremendous speedups to applications that can fully take advantage of it, but those applications are a small minority of all HPC programs (for the reasons I mentioned above). Those that weren't sped up, weren't slowed down either.
There are some cases compiling for AVX can slow things down slightly (see the link in my post above) due to the AVX offset of some Intel processors, though it's unlikely to be major problem.
Had he said that several of the test showed a improvement of >50%, it would at least have been a more accurate representation of the actual data
As might be expected, for larger systems the interconnect bandwidth and topology have an increasing impact but in our testing scenario limited to the single platform all such tests, do not show any advantage or disadvantage for AVX platform as in fact they are irrelevant for a single socket platform validation
No it would have been equally fallacious.
The current top Xeon is 22cores @ 2.4 GHz and is Broadwell based.
Broadwell is roughly comparable in IPC to Zen in throughput.
The top Zen Opteron will be 32C and could be at up to 3.0GHz.
As for specs, we're looking at up to 32 Zen CPU cores with 64 threads of performance, 64MB of L3 cache, a base clock of 1.4GHz and a turbo clock of 2.8GHz.
Read more: http://www.tweaktown.com/news/55836/amd-zen-based-naples-cpu-64-threads-128-pcie-3-lanes/index.html
http://arstechnica.com/information-...essor-more-cores-bandwidth-memory-than-intel/However, AMD is not currently offering clock-speed guidance, and the only benchmark it has demonstrated—a floating point-based seismic analysis workload—feels unsatisfactory. AMD compared a dual-socket Naples system against a dual Xeon E5-2699A V4 system. First the company handicapped the Naples machine by limiting it to 44 cores and 1866MHz memory; it ran the sample workload in 18 seconds, compared to Intel's 35 seconds. With the Naples machine using all 64 cores and memory at its maximum speed of 2400MHz, Naples finished the workload in 14 seconds.
These scores strongly suggest that the workload is almost entirely memory bandwidth constrained. At 44 cores and 1866MHz, the Naples machine has twice as much memory bandwidth as the Xeon, thanks to having twice as many memory channels; it also has almost exactly twice the throughput. The full strength (64 cores and 2400MHz) Naples machine shows a 29 percent improvement over the restricted one. The full strength machine also has 29 percent more memory bandwidth and 45 percent more cores. On top of all this, we know that Broadwell's actual floating point performance is, at least when using the AVX instruction set, about twice as much as Zen's at the same clock speed.
Finally, AMD offered a workload that quadrupled the size of the data set. The Naples machine completed the task in 54 seconds, while the Intel system crashed with inadequate memory. This proved convincingly that, yes, 2TB of RAM is more than 1.5TB of RAM.
So, you're comparing the base frequency of the Xeon (boosts to 3.6GHz) and against the rumored turbo of the Zen?
And having more bandwidth available is exactly the fault of whom?
Of course, like testing only AVX2 workloads (not AVX where the throughput should be comparable) paints a picture of Intel machines a little too bright.
Let's run the math using like to like, base-to-base and turbo-to-turbo:
[...] the only benchmark it has demonstrated—a floating point-based seismic analysis workload—feels unsatisfactory.
These scores strongly suggest that the workload is almost entirely memory bandwidth constrained.
In my business (automotive OEM's) people get fired for single sourcing of a supplier though.
In a mature competitive market it is very important to keep costs at a minimum by negotiating with all possible suppliers and buy the cheapest part that is good enough.
In my business (automotive OEM's) people get fired for single sourcing of a supplier though.
In a mature competitive market it is very important to keep costs at a minimum by negotiating with all possible suppliers and buy the cheapest part that is good enough.
Skylake-EP (Purley) has been available to cloud operators since Q4 2016. It has 6ch of DDR4-2666 (83% of 8x DDR4-2400 banwidth) and AVX-512.