we have measured ten contacted gate pitches as you can see, and that looks pretty close to the 70 nm that was announced by Intel back in August.
On another part of the bevel we can see the fins, and here we have counted 20 pitches (third image above). Which agrees with the 42-nm pitch in the Intel webcast. So far, so good!
A look at the edge seal (fifth image), which doesnt have the top metal or the MIM-cap, makes it easier to count twelve layers. We are used to seeing twelve-plus metal layers in IBM chips (their 22-nm Power8 has fifteen!), but Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip.
Intel quoted 52 nm interconnect pitch, but we see 54 nm (sixth image). Although that is within measurement error, and we may not have sectioned the most tightly packed part of the die.
As yet we dont have any detailed TEM imaging to look at the transistors or fins in close-up, so we cant verify if the fins have vertical walls or not, as shown by Intel (seventh image).
The cross-section seems to show that essentially the 14-nm process is a shrink of the 22-nm technology, with the modified fins; the gate metallisation looks similar to the 22-nm, with tungsten gate fill as in the earlier process. (As an aside, this will make it the fourth generation replacement metal gate process this technology has legs!)
Doesnt that look like a defect?
And where is AMD in all this?? Why are they still stuck on 28nm?? Or doesnt not matter once you get to a certain nm??
Oh very cool thanks.. so then will we see the successor to Kaveri in a 20nm flavor then??I wonder if Intel then will have a competitive IGPU/APU of there own pretty soon??
The successor to Carrizo is 14-nm, and so on.The successor to Kaveri is 28nm.
AMD from 2009 to 2011 was waiting for ET-SOI from GlobalFoundries.Why are they still stuck on 28nm?
This sort of explains why Carrizo is going for low power.Workshop: Fully Depleted SOI architecture, technology platform for Low Power applications for 22nm and beyond - Oct. 16, 2009 - Leuven, Belgium
The development of fully depleted SOI has gained strong momentum in recent years. Although initially FinFETs appeared to be a preferred FDSOI architecture, recent major advances in planar FDSOI devices are strongly positioning this technology towards an interception of the 22/20nm node for Low Power applications. From a design perspective, planar FDSOI is an evolutionary approach that is easier to implement than FinFETs. FDSOI CMOS has proved to reduce the Vt variability by 50-60%, makes possible the smallest SRAM cell operated at Vdd=0.5V with an excellent SNM, reduces Ioff by orders of magnitude and preserves a target performance at a cost per die that is comparable or lower than the equivalent bulk.
The transistor density of the Steamroller core on 28-nm. Is extremely near equal to the transistor density of Bulldozer and Piledriver cores on 32-nm.So AMD is going to drag us along with another 28nm release??
So AMD is going to drag us along with another 28nm release?? I hope they sorted everything out for there next FM2+ release. would be nice to see some improved IPC and speed bump while lowering TDP before they go Carrizo and a new socket.Otherwise this 14nm Intel is sounding kinda good. Maybe an i3 if they can increase the IGPU side of things.Any dates we can expect for either CPU?? I am looking forward to upgrading my 2 Media server HTPC's for 4K play back within the next 3-6 Months.DO you all think we'll see'em by then??
So AMD is going to drag us along with another 28nm release?? I hope they sorted everything out for there next FM2+ release. would be nice to see some improved IPC and speed bump while lowering TDP before they go Carrizo and a new socket.Otherwise this 14nm Intel is sounding kinda good. Maybe an i3 if they can increase the IGPU side of things.Any dates we can expect for either CPU?? I am looking forward to upgrading my 2 Media server HTPC's for 4K play back within the next 3-6 Months.DO you all think we'll see'em by then??
Doesnt that look like a defect?
don't they get these images by cutting into a chip? I imagine there is substantial damage and defect caused by that process.
Staining - uses heavy metals such as lead and uranium to scatter imaging electrons and thus give contrast between different structures, since many (especially biological) materials are nearly "transparent" to the electron beam. By staining the samples with heavy metals, we add electron density to it which results in there being more interactions between the electrons in the primary beam and those of the sample, which in turn provides us with contrast in the resultant image. In biology, specimens can be stained "en bloc" before embedding and/or later, directly after sectioning, by brief exposure of the sections to solutions of the heavy metal stains.
What is Electron Microscopy?
I wish I had enough money I can blow on pretty pictures of sexy technology. Then again those pictures for my use would be useless except art. If I had the money to buy such stuff I can probably find a better use for it than this even though it is coolor they are holding back the good ones for paying customers only.