<< There is quite a bit of info on Clawhammer as well.
Here are some details:
-256kb L2 cache
-103 mm^2 die
-67 million transistors
-.13u >>
The original K7 had 21 million transistors. Thunderbird added 256KB of L2 cache and has about 37 million transitors. This means 16 million transistors was spent on the L2 cache and the victim buffer. Let's apply this to Clawhammer. With only 16 million (estimate, but good enough for this calc) transistors for the L2 that leaves 51 million for the core, up from 21 million for the K7.
Hammer is based on the K7 design and contains quite alot of new features, but there is NO WAY those extra features adds up another 30 million transistors. Also consider the size of the Hammer die. 103mm^2 vs ~80mm^2 for Tbred. How on earth could you pack 30 million more transistors and into the die and only add a meager 20mm^2 if not most of these are high density L2 cache? The only resonable conclusion from this is that Clawhammer will have more L2 cache than 256KB... Probably 512KB. Either that or Jerry was lying about the 67 million number and I seriously doubt that.
By the way, do the calc for 1MB of cache for Sledgehammer and see what number you come up with and compare that with previous statements... Use Clawhammer 67 million as baseline.
<< I believe Intel only made it to 1ghz with the coppermine. They released a 1.13 ghz version but they recalled it. >>
Didn't Intel release a 1.1Ghz Celeron based on the Coppermine core? That was shortly before the Tualatin Celeron came out IIRC.