That's just your uneducated and irrelevant opinion.
Gameworks pushes PC gaming forward, GCN game console makes game devs extremely lazy and stuck in GCN2(1.1) era with no Conservative Rasterization, no Rasterizer Ordered Views, no Tiled Resources Tier 3.
Nvidia & Intel both support FL12_1 fully.
ONLY Intel Skylake has full (Tier) Feature Level 12_1 support., in fact nV's support of CR is minimal, so much so it BARELY meets the minimum requirement and falls far short of either Tier 2 or Tier 3.
While much is being made of DX12 Feature Level 1, it's ironic, given NV doesn't fully support ALL DX12 functions (as noted previously Skylake is the most complete D3D12 part currently)
with regard to conservative rasterization, even NV goes so far to point out that CR can be done w/o hw support..
https://developer.nvidia.com/content/dont-be-conservative-conservative-rasterization
Is it possible to achieve Conservative Raster without HW support?
Yes, it is indeed possible to do this, and there is a very good article describing it here.
Essentially it involves using the Geometry Shader
Edit: Would add that Tier 3 of Tiled Resources is merely Tier 2 with the addition of 3D Textures to Volume Resources (carried over from DX11.3), where as Resource Binding Tier 3 (supported on GCN) adds several increases in capabilities including
Max # of simultaneous tables containing SRVs, Tier 3 = Unlimited (vs 5 for Tier 2)
number of CBVs in (descriptor) tables, Tier 3 = full heap (vs 14 in Tier 2)
number of UAVs in (descriptor) tables, Tier 3 = full heap (vs 64 in Tier 2)
Max # of descriptors in heap for SRV, CBV & UAVs, Tier 3 1M+.
See
https://msdn.microsoft.com/en-us/library/windows/desktop/dn899110(v=vs.85).aspx
In summary, Tiled Resources Tier 3 adds only the ability for an extra axis (Z) where as Resource Binding Tier 3 adds a much greater capability in the ability for the GPU to access descriptors and the number of descriptors they can access.
TLDR: Tiled Resources (Tier 3 compared to Tier 2) < Resource Binding (Tier 3 compared to Tier 2)