Originally posted by: adairusmc
Originally posted by: BonzaiDuck
Adair -- I've bumped up my VCORE to 1.4125V and running at 3.2 Ghz. My high Core #0 load value at 74F/23C is pushin' about 60 to 61C. At 80F, the Core 0 would scale up to around 67C. Since you got such a big improvement lapping your U-120-Extreme, how am I doin'?
You are doing better than I am at 3Ghz, though I think that is mostly because the ambient temp of my computer room has been around 75-79F, depending on time of day.
I bumped my voltage up a little a few days ago, though my overclock was 13 hours Orthos stable, I had a random lock-up the other day. I bumped it to 1.31 and it seems to be running great (it is running an orthos test at home right now). I also switched to Zalman STG-1 thermal paste instead of the Arctic Silver 5 I have been using (ran out of the AS5, all we had was the zalman stuff at work).
Right now my idle temps are about 29C overall, core temps all in the low 40's. After a couple of hours of orthos, the load temps are about 55C overall, with core temps running around 65,65,62,61. To me that is still doing pretty good. I don't have any ducting mods, nor am I using that diamond thermal paste, which definitely gives you the temperature advantage. At the higher voltage, I was pusing almost 70C on the core temps, and the idle temp was around 38C before the lapping of the heatsink.
I probably could have lapped it better than I did (did not make it shine or anything, it was a dull copper color, but it was smooth and flat). I could not find any super-fine grit sandpaper at our local wal-mart at 10pm last night, so I used what I could get.
You don't need to make it shine. Some people are talking about using 2000-grit wet-or-dry and "Brasso" polish, but at that level of fineness, I don't think it matters. Either the silver or the diamond particles would work their way into the scratches anyway. When I lapped I stopped at 600-grit. Anyway, it's copper. With steel, you could make a mirror finish with 400-grit.
The ducting doesn't show up as much in the CPU temps. What my duct does is mostly to allow me to remove the fans from the heatsink and keep up the air-pressure between them, but this is an efficient cooler, and as long as the air exhausts right away, that part of the duct only helps as I said. I just wish I'd put a thermal sensor on the chipset, because that's where all the other case air is moving. I just checked, and room ambient was 79.1F. The hot Core 0 was bouncing between 63 and 65 with ORTHOS, and the TCase temperature is around 52. With the single core Prescotts, TCase was all you could see with monitoring software, and I considered it an accomplishment to get it down to around 43C with the room at 75F.
"TylerDustin" -- another member here -- is just up and running with a phase-change system. He had it CUSTOM-BUILT. I think he's going to freeze his processor. I think he will be better to run it just above freezing, because contrary to prevailing opinion, the silicon part of the CPUs don't behave like regular metal conductors. I bet he gets it to 5 Ghz!!
I learned a lot here in recent weeks. Unless there is a minor difference in chipset version, you have the same basic mobo ingredients that I have. Some people have been talking about "FSB holes," and today I discovered that all the thresholds on memory latencies that I'd found when running the E6600 processor have shifted -- downward. So when I expect that I need to loosen 3,4,4,8 to 4,3,4,8 at 372 Mhz, it seems that the threshold now is 358. this holds for the threshold between 4,3,4,8 and 4,4,4,10 -- also, now at 387 -- when reviewers using the E6600 C2D for testing said that 4,3,4,8 is good up to 425 Mhz.
I don't think there are any "holes." You just get farther with this processor at lower multiplier settings, if overclocking the memory and front-side-bus is part of the strategy. But from what I've seen with where the VCORE would go to get above 3.2, I think that's as high as it goes for me with multiplier=9. The load voltage with "droop" is around 1.36, or 1% over the retail-box Intel "Maximum." I think that's pretty safe -- hinging on how thoroughly INtel wants to avoid RMAs.
I'll probably try and start a topic on CPU&OC'ing about the latency threshold shifts with the Q6600. I can't quite put together the logic to explain it. I think it has to do with the L1 and L2 sizes for the respective Duo and Quad, and the cache bandwidth under over-clock, but you'd think that the shifts would move in the opposite direction.