CPU gurus? Enlighten me as to optimal CPU cache associativity.

[yllus]

Okay, been doing some extremely light reading on CPU cache properties recently with all the new articles on the design of the X-Box and other consoles out. I'm not mistaken, CPUs almost universally lean towards using the set associatively mapped caching system. Now, in Anand's Hardware Behind the Consoles - Part I: Microsoft's Xbox, he writes:

"The CPU that powers the Xbox is a Coppermine based Pentium III with only 128KB L2 cache. While this would make many think that the processor is indeed a Celeron, one of the key performance factors of the Pentium III that is lost in the Celeron core was left intact for this core. The Coppermine core was left with an 8-way set associative L2 cache instead of the 4-way set associative cache of the Celeron. Based on what we've seen with the Coppermine and Coppermine128 (Celeron) cores we estimate that the 8-way set associative L2 cache gives this particular core a 10% performance advantage over the Coppermine128 core of the Celeron."

I can't help but wonder what that could imply for my pitiful Celeron 466. I had always figured 4-way associativity was the optimal setup for a mere 128KB of L2 cache - but this X-Box neutering has put doubts in that. Is there any other significant difference between the X-Box's Cumine CPU and the Celeron128 I've got that would make 4-way better to use than 8-way?

I also vaguely remember an option in software (in wCPUid, I think) that allowed a user to edit the block associativity of his CPU, am I just imagining that or is that possible? Hell, if it's in my best interests to go to 8-way associative mode and actually possible to do, I'm there.

Thanks in advance.

 

[CTho9305]

good read. briefly mentions n-way associative caches

 

[kylef]

<< Is there any other significant difference between the X-Box's Cumine CPU and the Celeron128 I've got that would make 4-way better to use than 8-way? >>



Doubtful. Aside from the extremely rare (some say mythical) beast known as an "anti-conflict miss", MORE associativity is always a better idea IF cache latency is not a concern. The reason for this is simple: lower associativity causes more conflict misses.

In the real world, however, CPU designers have to trade-off the higher hit rates of large associativities and the better speed (and smaller transistor count) of direct-mapped and 1 or 2-way set-associative caches. Generally, they have used the former for L2 caches (which generally have pretty poor hit rates when taken alone but have more latency to play with -> ideal for a higher set associativity) and the latter for L1 caches (who get high hit rates but must be very fast, to return the hit within one or two clock cycles).

More probably in your case, Intel needed to differentiate the Celeron product line from the PIII. And, it is probable that the die size of the 4-way set associative cache is smaller, saving some $$ by improving the die yields.

The AMD Thunderbird, which seems to have a speed advantage to the Coppermine, uses a 16-way set associative L2 cache instead of an 8-way.

 

[MustPost]

<<More probably in your case, Intel needed to differentiate the Celeron product line from the PIII. And, it is probable that the die size of the 4-way set associative cache is smaller, saving some $$ by improving the die yields.>>

From what ive read they just use a laser to disable half of the L2 cache on a P3 to make a Celeron. This reduces the 8-way set to 4-way.

Doesn't the X-box use a pretty much normal mobile P3.

 

[JDJ]

<< From what ive read they just use a laser to disable half of the L2 cache on a P3 to make a Celeron. This reduces the 8-way set to 4-way. >>



I had also heard that in some cases there were P3 with crippled L2 cache, ie a portion of the 256k cache didnt work. To save $$ they took a laser to half the L2 as mentioned above and were able to 'recycle' chips that would have gone to waste.

- John