OK, I'll sketch it out.
Say, you need a stable clock frequency that can be switched from 800 to 1300mhz in 100mhz steps as needed.
The problem is that actual, real freq multipliers are hard to build without tuned circuits and such. Messy, constrained.
Instead, do this:
Start with a frequency reference. Make it an accurate 100 mhz source from a crystal oscillator.
Then make a tunable oscillator in the range of 800 to 1300. Its output will be the clock source for the CPU, etc.
Tap the output freq and run it though a count-down divider circuit (dividing is easy to do digitally) to a comparator.
Compare the output from this divider with your 100mhz reference.
Feed the comparator output error to the tunable oscillator control to correct the error. ( it will quickly freq lock and the phase will pull in to limit)
The output will be a stable frequency at some multiple of the reference oscillator, depending on the divider setting.
This is a "frequency multiplier" via a PLL. There are many ways to implement them, but this is the general idea.
And, the OP's question re higher mults. Generally, find a way to increase the PLL's divider count from , say 13 to 14, to increase the clock freq. Often the divider is indirectly controlled by loading a value from the bios or elsewhere into the PLL divider which sets the ratio. The bios in turn got that value from examining the CPU ID and furnishes the proper divider value. So, bios hacking could give great clock control up to the hardware limits, but that is easier said than done.