- Jul 5, 2001
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I think I'm starting to get an idea of what's happening inside my processor!
Here goes: The instructions travel through the processor's pipeline in five stages, 1)prefetch 2)instruction decode 3)address generate 4)execute 5)write back.
It takes five clock cycles for one instruction to be completed. But since its all being "pipelined" so that there aren't any empty stages, you can perform one instruction every cycle. Right?
The Pentium Pro is super pipelined. It's instructions travel through the pipeline in 14 stages. This means it has 14 instructions all going on at once, right? Is this faster then having just 5 instructions going on at once????
Plus I understand that the later Pentiums are superscalar. Does this mean they have two parallel pipelines churning out instructions at the same time????
Let me know where I'm mixed up.
Thanks.
Here goes: The instructions travel through the processor's pipeline in five stages, 1)prefetch 2)instruction decode 3)address generate 4)execute 5)write back.
It takes five clock cycles for one instruction to be completed. But since its all being "pipelined" so that there aren't any empty stages, you can perform one instruction every cycle. Right?
The Pentium Pro is super pipelined. It's instructions travel through the pipeline in 14 stages. This means it has 14 instructions all going on at once, right? Is this faster then having just 5 instructions going on at once????
Plus I understand that the later Pentiums are superscalar. Does this mean they have two parallel pipelines churning out instructions at the same time????
Let me know where I'm mixed up.
Thanks.