Possible 3D Vcache workload?Thank you for thinking about my computing environment.
One of my areas of study are the DNA chromosomes of perennial plants. My idea of a medium size chromosome is 20 to 30 MB -- literally a string of that length composed of the letters A,T,G,C. Per chromosome and per "marker", I need to perform 70 to 210 regular expression searches for substrings of size 16 to 512 letters, each of which will produce many coordinates of matches, all of which are then annotated and written to disk per search for post-processing. All of this is regular expression dependent and thus happening asynchronously.
For this application on a 30 MB chromosome and a single "marker", I clock the shortest total run time by paralyzing on the searches across 9 "kernels" on my 10 core CPU. For example, a total of 72 searches would be calculated by 8 iterations per kernel (a Mathematica dispatched process). The memory utilization for the first few minutes is about 80% of my 16 GB (according to Task Manager, incl. the OS) and then drops to about 70% for an hour or so, and then drops further as each kernel finishes its task. I estimate the OS and Mathematica memory overhead at about 17%.
Here's the specs:Possible 3D Vcache workload?
30 Mo is about the cache of a standard CPU, but if you're running multiple regexes it will definitely go way above that...
I'd be curious to see a perf differential between a 7950x and 7950x3D.
Python is not a functional programming language.Interestingly, I have a i7-5775C to see what 128MB of eDRAM cache would do in such workloads. Wish OP would cook something up quick in Python for me to benchmark
I know the specs, I'm curious about live testing a 3DV$ CPU on your kind of workload.
Python is not a functional programming language.
Following a paradigm doesn't make it not OOP.Functional Programming in Python: When and How to Use It – Real Python
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On an Epyc, I think it would be possible to create a CCD-aware application that uses all eight threads on one CCD and then uses the other CCD threads to preload data and request it much faster over the fabric when needed rather than going out to system RAM. Correct?I know the specs, I'm curious about live testing a 3DV$ CPU on your kind of workload.
I didn't. 🙂I know the specs
Sorry I can't help you there.I'm curious about live testing a 3DV$ CPU on your kind of workload.
I'll wager it could be done, likely involving assembly language. However, I'm not facing the bottleneck addressed by that approach.On an Epyc, I think it would be possible to create a CCD-aware application that uses all eight threads on one CCD and then uses the other CCD threads to preload data and request it much faster over the fabric when needed rather than going out to system RAM. Correct?
Very situational. Remember, bandwidth is still limited by the IF link to the IOD. EPYC has more than enough main memory bandwidth to aturate any individual IF link. You might gain a tiny but of first word latency from another CCD, but for any large dataset, it won't be useful.On an Epyc, I think it would be possible to create a CCD-aware application that uses all eight threads on one CCD and then uses the other CCD threads to preload data and request it much faster over the fabric when needed rather than going out to system RAM. Correct?
That's 20% of the cost of a warrantied system complete with liquid cooling. Then I'd need to purchase a CPU-locked Wolfram license to use it. Overall, a very poor use of my resources.Of course you can.
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Liquid cooling?That's 20% of the cost of a warrantied system complete with liquid cooling. Then I'd need to purchase a CPU-locked Wolfram license to use it. Overall, a very poor use of my resources.
You missed this in prior discussion:Liquid cooling?
For a 120W CPU?
Please check prior posts for answers.If you want corporate warranty, I don't really see why you came to ask us
LOL 😂HP or Dell
That's an uninformed response. Many individuals and institutions believe it is well worth the price.I think the problem is Mathematica.
You need to separate Stephen Wolfram's views on reformulating physical laws using cellular automata from the actual software his company makes.I think the problem is Mathematica. I've read a bit about the guy (he's a rare genius) and Wolfram Alpha was pretty impressive back in the day when I tried it. However, I believe he thinks that the world doesn't appreciate him or his contributions enough so he's resorted to overcharging for his abilities and products. This would be enough for me to never touch Mathematica because I dislike any company/individual engaged in price gouging.
It exists now in EPYC, but he has already said that is a bad solution. AND they have great L3 caches. Any Xeon would fade compared to EPYC.You need to separate Stephen Wolfram's views on reformulating physical laws using cellular automata from the actual software his company makes.
@Hermetian In one of your previous posts, you mentioned that ideally you would like to have a #of core:#of memory channel ratio of 1, right?
Lower end Xeon W 3500s based on sapphire rapids have models with that ratio of 2.
They boost to 4.8 GHz, but have a measly L3 cache.
The product you wish for may exist when Intel releases workstation Xeons based on upcoming architectures.
$5000 vs $1400.It exists now in EPYC, but he has already said that is a bad solution. AND they have great L3 caches. Any Xeon would fade compared to EPYC.
$1400 for what ? and if you are saying $5000, you are wrong. 9184x EPYC with 768 meg L3 cache is $1450 or less. 12 memory channels 4.2 ghz boost, 16 cores.$5000 vs $1400.
Hardly comparable.