This debate rages on exactly because no single number can characterize the whole pipeline, so it really boils down to what you think is actually important.
Talking about Zen1, if your code is coming from the instruction cache, passing through the decoders and not hitting any pipeline stalls, then it'll be limited to 4 instructions per clock.
If your code is coming from the uop cache and not hitting any pipeline stalls then it'll be limited to 6 uops per clock (notice that this may represent less than 6 instructions).
If your code has just the right mix of instructions and for some reason stalled waiting for operands (which may arrive either from memory or as results of other instructions) then in the best case you'll be able to issue 10 uops per clock (4 ALUs, 2 AGUs, 4 FPUs - the reservation stations seem to be mostly independent). Notice that in this scenario the CPU is working hard to compensate for the stall, it cannot sustain this issue rate forever.
If a number of instructions in your code have been executed but is waiting on the ROB to be retired (since it must be retired in order, a single slow instruction can hold the retiment of hundred others), then the retirement limit is 8 instructions per clock. Once again, the CPU is working to compensate a previous stall, it cannot sustain this retirement rate indefinitely.
I don't know why looncraz said that Zen2 is 8 issue. Mike Clark himself says it's 7-issue on the integer side alone: