Hellhammer
AnandTech Emeritus
- Apr 25, 2011
- 701
- 4
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Wow I should have read that diagram more before my post. What process are they doing that on? That is just terrible endurance.
Based on the die size and memory array efficiency the cell size of Intel/Micron 3D NAND is about the same as Samsung's V-NAND.
Process nodes are actually very tricky because all the numbers you see are nearly always just marketing figures i.e. the smallest feature size in the die. By that definition, Samsung V-NAND is actually ~21nm, but the cell half-pitch is 3Xnm. Context is the king because a process node without any details doesn't tell what is measured. Hence cell size describes cost efficiency and endurance characteristics much better.
Intel-Micron's floating gate design is also inferior to charge trap because it requires higher operating voltages, which cause more stress on the cell structure and hence lower endurance.