Delidded my i7-3770K, loaded temperatures drop by 20°C at 4.7GHz

[exar333]

I must be doing something wrong. The AS5 which tested fine when I first applied it, only lasted 10 days before my temps were about 15C higher. I've swapped back to NT-H1, but this is somewhat baffling. Is there something about the thermal expansion and contraction on these chips that just makes normal paste stop working properly.

We'll see how long this NT-H1 lasts this time

I'm wondering if my H100 doesn't have some issue, and when I remove it and put it back on, I am shaking the pump loose or whatever.

AS5 is not great in it's ow right. I used NT-H1 for years and it was fantastic (X58 build). I ran in the 60's/low70's for my 920 and did not need to reseat the TIM for the 2+ years I had this build.

I have been using IC7 on my X79 build, and saw a good 5C decrease in temps compared to NT-H1 (allowed this seat for a few days too). IC7 is very thick, but doesn't need much time at all to reach peak performance.

 

[Ferzerp]

AS5 is not great in it's ow right. I used NT-H1 for years and it was fantastic (X58 build). I ran in the 60's/low70's for my 920 and did not need to reseat the TIM for the 2+ years I had this build.

I have been using IC7 on my X79 build, and saw a good 5C decrease in temps compared to NT-H1 (allowed this seat for a few days too). IC7 is very thick, but doesn't need much time at all to reach peak performance.

Well, since the thread is so long, I'll restate the issue because it is easy to miss.

It seems that whatever I use works great initially, (with my settings, peaks in the mid 60's in IBT). However, from a few weeks to a few months of use, temps end up 15-20C higher than when I started. NT-H1 has done it twice, AS5 has done it once. I'm back to NT-H1 now, but I expect I'll have to re-do it in a month or so. Something is odd about the way TIM under the IHS acts over time. I've seen it repeatedly, and someone posted a link to a hardocp forum post where someone there sees it too.

Maybe this is why the chose what they did under the IHS?

 

[BonzaiDuck]

Well, since the thread is so long, I'll restate the issue because it is easy to miss.

It seems that whatever I use works great initially, (with my settings, peaks in the mid 60's in IBT). However, from a few weeks to a few months of use, temps end up 15-20C higher than when I started. NT-H1 has done it twice, AS5 has done it once. I'm back to NT-H1 now, but I expect I'll have to re-do it in a month or so. Something is odd about the way TIM under the IHS acts over time. I've seen it repeatedly, and someone posted a link to a hardocp forum post where someone there sees it too.

Maybe this is why the chose what they did under the IHS?

Whatever they chose -- and IDC presented some pictures to suggest its consistency and putty-like quality -- it was designed to avoid "Voids." Since I've said several times that IC Diamond has a similar putty-like quality, it will be great if IDC follows through with his tests, or if someone else also goes forward with it.

I'd do it myself, but I won't be ready to make outlays of $700-something for parts to build an IB "K" system until after September . . .

 

[rge2]

Apparently Shin-Etsu X23-7783D has been used as TIM1 in some cpus, and was used as a control in one white paper, so thick pastes may work better. Though i would still try to have as little space as possible between IHS and die.
paper from enerdyne who make tim1 solutions: http://www.enerdynesolutions.com/downloads/thermal_imaps_atw_2005.pdf

quote from same paper suggesting tim1 represents now ~50% temp gradient from junction to case.

With average processor core-level power densities approaching 300 W/cm2 and nearly 50% of the overall processor junction-to-case thermal resistance budget consumed at the first level thermal interface (TIM1), the use of an all-metal interfacial thermal path is highly desirable. Phase Change Metallic Alloys (PCMAs), unlike eutectic solders, are well-suited as a TIM1 thermal interface between materials of dissimilar Coefficients of Thermal Expansion (CTEs), such as a copper lid and silicon die.

 

[Ferzerp]

I actually sanded the IHS stand off portion down such that I don't even have space between the die and the cpu unless the clamping force from the socket flexes the IHS and warps it over the die.

 

[ehume]

Is this thread still going?

OP is on vacay. We are patiently waiting his return, whiling away the time while we do.

 

[BonzaiDuck]

OP is on vacay. We are patiently waiting his return, whiling away the time while we do.

Well, I thought there were at least two others in the "Cap Poppin' Club" who've posted some actual firsthand results here. We're all sittin' on pins and needles . . . .

 

[ehume]

Well, I thought there were at least two others in the "Cap Poppin' Club" who've posted some actual firsthand results here. We're all sittin' on pins and needles . . . .

Is that what you're using for TIM now . . .

 

[lesd]

Another positive data point with an IHS paste replacement.

Delidded my 3570K, ran it with NT-H1 (both CPU->IHS and IHS->HSF), then with Coolaboratory Liquid Ultra. Applied the liquid ultra to all 4 surfaces before assembling.

Heatsink is a Noctua NH-C12P. Case has limited airflow, so temps are higher than other results I've seen.

Test run at 1.235V, 4.3GHz.
Max temp on hottest core during IBT "High", 10 runs:
Stock Paste: 96C
NT-H1: 89C (-7C)
Coollaboratory Liquid Ultra: 78C (-18C)

 

[Idontcare]

My concern is the Liquid Pro dripping down out of the cpu and causing a short.

Mite have to get some black rubber epoxy and seal up the bottom and sides at least so if any escapes it stays inside the IHS.

Another concern is the Liquid Pro itself and how it is applied. From what I've read, Liquid Pro is mainly used for surfaces that need very little 'filling in' of the gaps (mainly for flat surfaces - so the die qualifies, not sure about the IHS and any concave/convex issues), where Liquid Ultra is less liquid form and more paste form and designed to 'fill-in' the gaps. Having said that, my concern is that if there is any air gaps between the naked die and the IHS, this will easily burn out the die ? I guess you could do a test apply and check the spread, but that still doesn't ensure you have any air gaps. I guess that is why a TIM in paste form would be 'safer' in this regard as it designed to fill-in those air gaps better than say Liquid Pro ? Any thoughts on this ?

IDontCare mentioned when putting the IHS back on, you need to watch out for shorting the IHS on the PCB standoffs or something ? Im not sure here. Do you mean the exposed gold contacts sitting on the PCB ? If this is the case, does IHS need to be placed on the PCB so as to avoid the gold contacts all together OR does one need to cover the gold contacts and hence make it even all the way around, then place the IHS on ?

Very awesome thread BTW.

The die itself is completely electrically sealed and isolated from the top-side except for the three rows of landing pads located at the very edge of the PCB.

So long as you do not get so sloppy to the point of getting liquid metal TIM dripping over the edge of the PCB and down into the socket itself, the biggest concern you have is to keep the IHS itself off of that nearest row of landing pads (because the IHS does slide around a bit when you latch the CPU into the socket after delidding and relidding).

Based on what I have seen so far in terms of how far the TIM spreads when relidding the IHS, I am not at all worried about shorting. I am still a little concerned about cracking the die though.

I like your idea of covering the pads themselves as a means of mitigating the risk here, perhaps with black electrical tape?

So far I just take great care in positioning the IHS such that when it is all done being pushed around by the socket retention mechanism it (the IHS) just happens to not be on top of those landing pads. It is a bit tedious but so far I haven't had any issues making it work out.

<snipping out an equisitely succinct analysis posited on the basis of solid deductive reasoning>

So, my belief is that the lines intersect, and that's why we can't overclock i7-3770K any more than Sandy:

Please fix my drawing. I want to be educated!

:thumbsup: I had not considered this before but I have to totally agree with you! Excellent layout of your position by the way, truly top-notch stuff there

It could well be the case here where Intel intentionally targeted their 22nm Idrive such that they would just ever so slightly eclipse the clockspeeds of 32nm while maximizing the reduction in power consumption to focus on driving AMD out of the mobile markets as well as advancing their (Intel's) plans to position 22nm Atom in the handset market.

And you are right, astute observation there, Intel has NOT touted their Idrives for 22nm as they had so prominently done in the past with prior nodes. That absence is very telling and may well explain the observations we are making here.

Another positive data point with an IHS paste replacement.

Delidded my 3570K, ran it with NT-H1 (both CPU->IHS and IHS->HSF), then with Coolaboratory Liquid Ultra. Applied the liquid ultra to all 4 surfaces before assembling.

Heatsink is a Noctua NH-C12P. Case has limited airflow, so temps are higher than other results I've seen.

Test run at 1.235V, 4.3GHz.
Max temp on hottest core during IBT "High", 10 runs:
Stock Paste: 96C
NT-H1: 89C (-7C)
Coollaboratory Liquid Ultra: 78C (-18C)

Welcome to the AnandTech Forums lesd :thumbsup: I'm glad to see you used the Liquid Ultra as there was some question earlier as to why it seemed like most folks were opting to use the Pro instead of the seemingly superior (on paper) Ultra product.

Did it apply just fine for you? Any trickiness to it?

 

[Idontcare]

..

I happen to live right outside Ocean City, MD! I am a long time member @ [H]ardforum, and have been following this thread since you first started it..

I will have some data on my 3770K, which has been delidded since I got it back in June..

I have a pure copper WB (Enzotech Sapphire, one of the best still) that is mounted directly to the die..I am currently using MX-2, and once I see where my temps are, I will report back with o/c, temps etc..

Welcome to the AnandTech forums C.C. :thumbsup:

That MX-2 TIM, is it like a putty or is it more like a liquid gel?

With a great WB like that, I have to imagine your load temps are very nice.

 

[lesd]

The liquid ultra wasn't too tricky, just used the little brush in the package and applied just like the CoolLabs youtube video. I did it on the die, both sides of the IHS, and the bottom of the heatsink.

I did read somewhere that the LiquidPro actually has better thermal conductivity than the LiquidUltra, but the Ultra gave me pretty nice results as you can see.

P.S. - I used the hammer method to remove my heatspreader. Worked like a champ!

 

[C.C.]

I was really trying to defer posting this, but it's just a suggestion. I had heard of MX-2 maybe five years ago when I had already graduated from AS-5 to "home-made diamond" and finally IC Diamond. I failed to investigate further the composition of MX-2, figuring it was just another OEM's thermal paste, bundled with a heatsink, or generally available as a "satisfactory" TIM.

Since I don't have any data on MX-2 and you are using it, it would be useful [for somebody] to see a comparison [controlled hardware, speed, ambient temperature] with IC Diamond. I only say this because MX-2 has been promoted as carrying carbon, carbon-compound or carbonized particles:



About the time I discovered micronized diamond, a news article reported an asian-american lady researcher who had discovered ways to make the cheaper forms of carbon into TIM slurries, pastes, oils etc. which reduced thermal resistance and increased thermal conductivity.

Of course, micronized diamond is carbon in crystallized form, and the paste made by Innovative Cooling is so loaded with diamond that it spreads like drying concrete on a warm day.

I have used MX-2 since it first came out, from the Athlon 64 days to current..It is easy to apply, and I have never had to reapply it unless I took a build apart...

That being said, I would be happy to purchase some of this IC Diamond as long as you guys don't think it will "drip out" from between the die and my cpu block..I am a little worried about that since I am not using the IHS..(which if I were I would reseal as others have mentioned)..

Finally, if you guys think it will acceptable to use in my application, where is the cheapest place to order it from, considering I am in MD?

 

[C.C.]

Welcome to the AnandTech forums C.C. :thumbsup:

That MX-2 TIM, is it like a putty or is it more like a liquid gel?

With a great WB like that, I have to imagine your load temps are very nice.

Thanks for the welcome! How did you enjoy your vacation? You picked a good time to leave..It has been raining cats and dogs for the last 24 hrs! It is currently raining so hard I can hear it bouncing off my back patio..

The MX-2 is more of a liquid gel then a putty..I have my loop torn down atm, since I was making some home made noise blockers for my HAF 932..I should hopefully have it back together in the next few days..This weather loves to affect my migraines, and saps my motivation

 

[lesd]

Found the thread with the discussion of Coolaboratory Liquid Pro vs. Ultra thermal conductivity!

See post #298 near the bottom of this page:
http://www.xtremesystems.org/forums...ovals-CPU-temp-dropped-from-79C-to-71C/page12

Hopefully linking to another site is OK - didn't want to just cut and paste.

 

[mrob27]

It could well be the case here where Intel intentionally targeted their 22nm Idrive such that they would just ever so slightly eclipse the clockspeeds of 32nm while maximizing the reduction in power consumption to focus on driving AMD out of the mobile markets as well as advancing their (Intel's) plans to position 22nm Atom in the handset market.

Yep, that's basically my conclusion too. They're not making lots of friends with this strategy, but I can't blame them for giving priority to the mass market.

But I see hope. In 32nm and all previous fab processes, Intel has always developed a second process on the same node, usually about a year later:

(Source: This and the following are all from Baker's presentation at IDF, 2009 Sep 22)

The basic strategy from the fab standpoint is to start with a mainstream process that will give the highest yields, but has a narrow range of capabilities. Once that is working, then tweak the fabrication steps to allow for a wider variety of electrical characteristics (like the all-important Idrive). This is done 2-3 years in advance, then "Copy Exactly!" is used to deploy it in the production fabs.

The follow-on "SoC" process is mostly used for products like Rosepoint, the Atom with the Wi-Fi radio on the same chip. However, they can also be used to offer a greater range of "low lower" vs. "high performance" transistors (upper-left in this image):

Most of this requires work on the basic chemistry and optics of the silicon fab process. Relatively less can be accomplished with a CPU "stepping" — typically rewiring critical paths in pipeline stages, doubling a transistor to boost fanout, etc.

Regarding 22nm specifically, we also know that Intel has experimented with different sized SRAM cells:

There are no Ivy Bridge high-performance CPUs yet: all Xeons and i7-Extreme are still on 32nm (no, I don't count the 4-core Xeon 1600 series, but it is notable for having a 4.1 GHz turbo speed at stock settings).

So my optimism rests on the possibility that Intel decided to aim P1270 (the first 22nm process) at a slightly lower-voltage, lower-performance transistor performance curve. That would imply that they're saving the higher-performance capability for P1271, and future Ivy Bridge-based Core i7 Extreme or two-socket Xeons will use it.

 

[Idontcare]

Found the thread with the discussion of Coolaboratory Liquid Pro vs. Ultra thermal conductivity!

See post #298 near the bottom of this page:
http://www.xtremesystems.org/forums...ovals-CPU-temp-dropped-from-79C-to-71C/page12

Hopefully linking to another site is OK - didn't want to just cut and paste.

Of course it is OK to link to other forums. Haven't read the link yet but I will, thanks for sharing it :thumbsup:

Thanks for the welcome! How did you enjoy your vacation? You picked a good time to leave..It has been raining cats and dogs for the last 24 hrs! It is currently raining so hard I can hear it bouncing off my back patio..

The MX-2 is more of a liquid gel then a putty..I have my loop torn down atm, since I was making some home made noise blockers for my HAF 932..I should hopefully have it back together in the next few days..This weather loves to affect my migraines, and saps my motivation

Vacation was awesome, weather was not so great (as you know ). But we did get a couple good sunny days on the beach though. And the food is always great, rain or shine, so that was wonderful too (Tuna at Harpoon Hanna's, Nick's Ribs, all-u-can-eat snow-crab at the Bonfire ^_^)

Hope you get the sun back so the migraines go away and you feel better.

So my optimism rests on the possibility that Intel decided to aim P1270 (the first 22nm process) at a slightly lower-voltage, lower-performance transistor performance curve. That would imply that they're saving the higher-performance capability for P1271, and future Ivy Bridge-based Core i7 Extreme or two-socket Xeons will use it.

That's exactly how we did it at TI (Texas Instruments) as well. We had three sub-nodes, much like TSMC, which were staggered in release timeline going from mobile/low-power first and on to mid-power and then high-power about a year or 18 months later.

All our mobile chips went on the lower-power subnode, then our basebands and high power DSP's went on the mid-node (launched about 6-8 months after the mobile subnode), and all of SUN's microprocessors went on the highest powered node albeit delayed by about 18 months from the release of the mobile node.

The reason for the timeline stagger was completely due to internal priorities, management wanted the high volume devices in the fabs first and that meant getting the mobile subnode into production first. The lower volume stuff, specialized DSPs and SUN's chips, always played second fiddle despite the margins being so much higher.

Intel could be doing the same thing for the same reasons, albeit with just two subnodes versus three that the foundries typically roll out. In which case there is a good chance that Haswell was designed on the basis of being produced on the higher-performing subnode versus that which IvyBridge is produced.

 

[Idontcare]

Finally, if you guys think it will acceptable to use in my application, where is the cheapest place to order it from, considering I am in MD?

I ordered some to test on my 3770k, BonzaiDuck referred me to Sidewindercomputers which I then ordered from. It came quick too, shipped to PA and I had it in maybe 4 days tops after ordering.

 

[BonzaiDuck]

I ordered some to test on my 3770k, BonzaiDuck referred me to Sidewindercomputers which I then ordered from. It came quick too, shipped to PA and I had it in maybe 4 days tops after ordering.

Just to be clear on this item . . . Ehume in an earlier post had asked "Is that what you're using for TIM now . . . " and I thought he was making a joke off what I'd said about "sitting on pins and needles" as we anticipate results from these different TIM choices.

As much as I jumped on the diamond bandwagon during the months in which IC Diamond was released, I did it because it simply works, and it works simply because the key ingredient has a thermal conductivity many times higher (or thermal resistance many times lower) than silver [which, in turn, outranks copper -- but by a less significant margin].

I would choose any TIM over another based on these features. However, the liquid-metal or indium-based products outstrip diamond by only a few degrees in the temperature reduction. Such an improvement would still drive my choices, but for my most recent Sandy Bridge build (now a year old), I used what I had available.

The issue now has two aspects: thermal cycling and its effects on liquid-metal and the safety of the silicon die; and the "pumping-out" effect with less viscous silicon-grease formulations and products.

I am hopeful about IC Diamond for a couple reasons:

-- the oils it contains are going to dry out (more or less) anyway.
-- the solids -- namely the micronized synthetic diamond particles -- are not going to pump out.
-- we've seen a few strong arguments, albeit from IC reps, that the 2-micron particles are not going to damage the silicon die, or that they [Innovative Cooling] had used the formula several times for direct-die applications.
-- the residue of the IC Diamond seems to have a consistency or material qualities resembling the original Intel TIM.

To make "de-lidding" a viable approach to the Ivy-Bridge processors for enthusiasts, the TIM choice cannot leave us with a regular maintenance chore of refreshing it after two weeks -- when some TIM choices show a severe degradation in their effectiveness [because of "pumping out" -- what seems to be the only practical explanation.]

ADDENDUM -- JUST AN AFTERTHOUGHT: I can imagine a solution that deploys one TIM for the IHS-to-die contact, and a different TIM for the mating the HSF to the IHS. Thus, if we find a problem with the metal-pro and discover something "less risky" but almost as effective, the most effective TIM could still be used for its originally-intended purpose.

 

[Ferzerp]

Just how much of the impartant bits are that close to the face of the die anyway? I mean nvidia etches their logo and the part description directly on to their die. I can't imagine they'd do so if the inherent nature couldn't handle it. That is, they wouldn't make it thicker just to etch the logo.

 

[BonzaiDuck]

Just how much of the impartant bits are that close to the face of the die anyway? I mean nvidia etches their logo and the part description directly on to their die. I can't imagine they'd do so if the inherent nature couldn't handle it. That is, they wouldn't make it thicker just to etch the logo.

Which speculated risk are you addressing with your question? It's a useful question. To which -- I have no specially inspired answers.

I guess we're going to find out, one way or the other.

 

[Ferzerp]

Which speculated risk are you addressing with your question? It's a useful question. To which -- I have no specially inspired answers.

I guess we're going to find out, one way or the other.

The worry of die damage with a paste filled with hard elements. I'm not so sure that any marring of the surface would be detrimental to the cpu anyway, but I don't know.

 

[Idontcare]

Just how much of the impartant bits are that close to the face of the die anyway? I mean nvidia etches their logo and the part description directly on to their die. I can't imagine they'd do so if the inherent nature couldn't handle it. That is, they wouldn't make it thicker just to etch the logo.

There are no important bits close to the surface that we are interacting with because the surface we see is actually the backside of the die.

The concern we have is that of crack propagation. (highly recommend checking out the link)

We don't want to create a stress concentrator on the backside of the silicon die (a brittle material below 500°C) which then exceeds the fracture toughness and critical crack length for the die itself, causing the crack to propagate through to the other side which does contain the important bits.

 

[Ferzerp]

ahh, ok.

 

[BonzaiDuck]

The worry of die damage with a paste filled with hard elements. I'm not so sure that any marring of the surface would be detrimental to the cpu anyway, but I don't know.

The point had been made that 2-micron diamond particles are so small, that there are going to be billions of them between the two surfaces to distribute weight or pressure, that they're not going to "move around." I originally threw out the question about these risks, but I now count them as minimal -- or smaller.

IDontCare had originally raised the question of risk from a metallic product that changes states, introducing more aspects of different thermal expansion properties and so on.

I'd be eager to put my own money into an IB chip just to participate in testing here, but have reasons for not doing so until later this year.

Also, I think it will be important to track the different "experiments" through a couple weeks or more of usage, reviewing again how the thermal data stacks up over time.