[Digitimes] AMD prepares Zen for CES 2017 launch

[swilli89]

I feel sorry for the user

I would pay money to know what you're like in real life. You are easily the most tireless campaigner I've ever witnessed in all my years of reading forums. Amazing.


Personal attacks are not allowed
Markfw900

 

[Dresdenboy]

What would that fix? Remember Zen got SMT too.

Its not just the thread jumping that's the issue, its also the cluster to cluster communication for MT loads. Just as on the consoles. For the MCM clusters and SMP on top for a 2P server. I feel sorry for the user

Of course, SMT is good. With logical core renaming (lets abbreviate it with "LCR") a MPU might OS-independently group up to 8 threads with heavy inter-thread communications onto one CCX. This might even be faster than running them on 2 CCXs, one per core. Same for grouping onto the same die. Those use cases can quickly be extended to app power optimizations, as freeing CCXs or whole dies from threads could be used for power gating the unused silicon. And reducing inter cluster communications saves power as well.

But those scenarios depend on several unknowns, e.g. all the latencies.

 

[ShintaiDK]

Of course, SMT is good. With logical core renaming (lets abbreviate it with "LCR") a MPU might OS-independently group up to 8 threads with heavy inter-thread communications onto one CCX. This might even be faster than running them on 2 CCXs, one per core. Same for grouping onto the same die. Those use cases can quickly be extended to app power optimizations, as freeing CCXs or whole dies from threads could be used for power gating the unused silicon. And reducing inter cluster communications saves power as well.

But those scenarios depend on several unknowns, e.g. all the latencies.

But wouldn't that be a performance limitation as well for the end user. And what about those applications you cant restrict to a single CCX that isn't something like a tile based renderer?

It quickly gets very ugly. That's why you could end up with a better experience on a single CCX CPU than a double CCX, even when clocked the same in some cases. We know from consoles how big the issue is there. It also explains some of the GB3/4 massive scaling penalties we see.