It's based on real disclosed information. So TSMC gave information about their process nodes and Intel used its internal information to make this slide. So unless TSMC changed their process, this is how it will be.
That's an Intel PR slide, so I do not put to much trust into that. As other have noted, there's a PR slide war at the moment between GF/Samsung/TSMC/Intel/[...].
Also, note the "*" symbol in the slide indicating it's a "Forecast". I.e. wild ass guess made to make Intel's process tech look better than the competition...
So you don't have a source, despite that you made the claim in this thread? As expected...
Or put another way:
TSMC/Samsung: "Look guys, we've massively lagging been behind for the last years. I don't know how that happened, but now we're going to suddenly catch up, although we're only half the revenue of Intel and Moore's Law is getting more expensive."
That's called investment, and this has only happened in the last 5-7 years (at least on this scale), which gets us back to the extraordinary boom of small devices called "smartphones".
Samsung and TSMC may be half the revenue of Intel, but exactly as Intel has invested to create smaller chips that can go into smartphone 5 years ago, foundries have invested to make sure they were not thrown out of the market when Intel finally makes a competitive design (which for smartphones they still don't have but they are closer than ever).
It's as simple as that, both sides are converging, which one is going to be first is up for debate but the past does not always give an indication of the future.
And if you are late and still have money left (which at the moment all the players have), you can still lower your prices to keep a foot in the market until you catch-up.
You have a point here obviously. At least they didn't call it 20nm.Based on that slide, was it wrong for Intel to call their 22 nm process 22 nm? Because it's only as dense as TSMC's 28 nm. So maybe Intel should have called their 22 nm process 28 nm instead?
It's based on real disclosed information. So TSMC gave information about their process nodes and Intel used its internal information to make this slide. So unless TSMC changed their process, this is how it will be.
Well what about this slide by TSMC:
Seems like they disagree already?
Thank you for your message. Regarding your question about the area scaling chart, the plot is qualitative since no one has the actual data. That said, the 15% area scaling from 20nm to 16FF is made possible by optimizing our 16FF rules to provide smaller cells which can reduce chip area. Meanwhile, I would like to point out one dimension that has not been captured in this graph, and that will be "timing" for the nodes. The reason the area gain on 16FF vs. 20 SoC is smaller compared to other node-to-node transition is because we have decided to leverage our 20SoC product ramp experience and make 16FF ready sooner. Please note that the timing difference between our 20SoC risk production and 16FF risk production is only one year (instead of the typical 2 year gap). However, we will be very aggressive on 10nm in density and performance, which is captured on the graph. Currently, in our roadmap, 10nm will follow 16FF in 2 years. I hope the above clarification is helpful.
You have a point here obviously. At least they didn't call it 20nm.
But the main thing you have to keep in mind is that node names are just names with no meaning.
You don't decide the rules as to what gets to be called a new node. Bleeding edge process development is hard and risky. TSMC and Samsung are moving from 28nm planar to 16/14nm FINFET in a couple of steps to reduce risk. First they bring a 20nm planar with close to 1.9x density increase and then move to FINFET with 15% density increase.But that doesn't mean that the underlying meaning is gone. If you call something a new node, you can expect that it is a big upgrade with 2 improvements:
1) Better transistor
2) Smaller transistor
That's not what TSMC's 16nm or Samsung's 14nm does. They comply with the first point, but you don't get the second improvement. So nodes aren't comparable cross company, and now they even won't be from the same company, because you don't get the expected improvements.
rubbish. each company is pursuing Moore's law in the way they see best fit. Intel went FINFET first at 22nm and then double patterning immersion litho with FINFET at 14nm. TSMC/Samsung have made the transition from 28nm to 16/14nm a 2 step process. 20nm planar with dual pattern immersion litho first and then FINFET later. We will see over the next 2 years how each player's strategy worked.So between companies, there could be variables. TSMC is more focused on density (28nm), while for Intel, performance and power is more important (22nm) (they implement technologies 1 node earlier).
But if you compare 22nm to 32nm, you'll see that 22nm does give a meaningful improvement in density (1.7x or so). Further, Intel was bottlenecked because they wanted to keep using single patterning. But they'll make up for this at 14nm.
In the end, Intel is nicely following Moore's Law like it should. TSMC, Samsung and GlobalFoundries aren't. So while you could say that they have the right to do this because node names don't mean anything and Intel's density is/was less than you'd expect, it just isn't consistent so it misleads people. If you want real information, you should compare transistor characteristics instead of names, which is not what you're doing.
By the way, another reason why TSMC seems to be doing this is because focusing on density doesn't yield the satisfied results anymore.
And Intel data for their own process on that slide is marked as "forecast" for both 14nm and 10nm. This makes the slide uninteresting IMHO. Let's wait for IDF presentationsIntel stated the source of their information about TSMC's process. So it should be correct, unless TSMC disclosed wrong information about their process.
That must be the worst article I've read in quite some time. If we take the fin, for example, 1nm is about 0.4 Intel nm. The worst about the article is that it only mentions Intel. You should take more objective articles as your source.Given Intel's node names have been misleading thats how it is
http://www.electronicsweekly.com/mannerisms/general/the-intel-nanometre-2013-02/
If you want to move to a new node in 2 steps, that's fine, but the node you call the 2nd step should only be 1 step lower, not 2.You don't decide the rules as to what gets to be called a new node. Bleeding edge process development is hard and risky. TSMC and Samsung are moving from 28nm planar to 16/14nm FINFET in a couple of steps to reduce risk. First they bring a 20nm planar with close to 1.9x density increase and then move to FINFET.
Sure, but don't call something a new node (an advancement of Moore's Law) when you have only half the improvements necessary to do so, certainly when the density is the same.rubbish. each company is pursuing Moore's law in the way they see best fit. Intel went FINFET first at 22nm and then double patterning immersion litho with FINFET at 14nm. TSMC/Samsung have made the transition from 28nm to 16/14nm a 2 step process. 20nm planar with dual pattern immersion litho first and then FINFET later. We will see over the next 2 years how each player's strategy worked.
And Intel data for their own process on that slide is marked as "forecast" for both 14nm and 10nm. This makes the slide uninteresting IMHO. Let's wait for IDF presentations
There is no rational explanation for calling 20FF 16nm. But that's what marketing has come up with.
I already explained this.Did you call Intel 22nm as 28nm given that Intel had no significant density advantage over foundries 28nm. So just leave it.
I don't know how many times I've used this great article, but here's the most important quote:
TSMC:
Another nice thing that I didn't remember is that this statement confirms a 2018 release of 10nm.
Did you call Intel 22nm as 28nm given that Intel had no significant density advantage over foundries 28nm. So just leave it.
For comparison Intel 22nm SRAM cell size is 0.092 µm2 . If Intel can get SRAM cell size below 0.05 µm2 it would be praiseworthy.
Density = transistor count / area (mm²)Guys, unless you produce the same IC in both processes you will never find out which one is more dense than the other.
Density = transistor count / area (mm²)
Sure we can.
And, there's not a damn thing the fabs can do to stop them.
I think, in part, that Intel is keeping the pedal to the metal on process node delivery because they will soon price everyone* out of the mid to high end phone SoC business. By that I mean, the SoC design costs at 10 or 7nm will become prohibitive to every one else. Other companies will not be able to sink a billion dollars into a new SoC - if they sink $500M in, they will end up with much lower xtors/mm2**, bloated die sizes and lower performance. That will still leave hundreds of millions of low-end phones out of the reach of x86 - but Intel has SoFIA for that (and eventually, that will likely go away).
Intel will price it's x86 SoC below market as needed to get the design wins they need. This is simply a page taken from Robert Noyce's playbook (co-founder of Intel) when he dropped the prices of early Fairchild ICs below cost which increased volumes to the point where economy of scale brought them back to profitability (because lower costs opened up vast new areas of application).
* Apple, who can clearly afford the design costs, will likely become an Intel Fab partner so that they can maintain control over their design an maintain an alternative ecosystem so that they can keep their profits high. Love them or hate them, it's working for them so far.
** They will not be able to come close to the xtors/mm2 defined by the PDK. Intel will do much better at reaching PDK limits.