[DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

[Arachnotronic]

I can accept their 10nm timeline, it is reasonable. But I find it difficult to accept their claims of matching or near-matching Intel's parametric FOM and design rules.

I agree. At 16FF/16FF+ they're at 90nm gate pitch, matching Intel's 22nm. 64nm minimum metal, which is ahead of the 80nm minimum metal Intel had at 22nm, but both well behind the 70nm/52nm of Intel's 14nm.

That said, TSMC claims a 2.2x gate density improvement in going from 16FF+ -> 10nm, so if we look at the metric GP*MxP, then TSMC will go from (90)(64) = 5760 -> (X)(Y) ~= 2618

Assuming they scale metal + gate pitch roughly equally, then the pitches should be:

GP = 60nm
MxP = 44nm

If we take Intel's 14nm and scale by a factor of 2 (Intel claims >2x density improvement over 14nm at 10nm, but I want to look at the "best case" for TSMC), then we go from 70nm GP -> 49nm, and then in metal we go from 52nm -> 36nm.

Realistically, though, Intel already made a big jump (>2x) in metals at 14nm and was behind 2x scaling with gate pitch, so I think Intel will reverse that (go >2x with gate, and ~2x with metal).

At any rate, assuming 2x scaling for both min metal and gate pitch gives us the 49nm GP and 36nm minimum metal, which should mean the GP * MxP metric for Intel 10nm winds up at (49)(36) = 1764

1764/2618 = 0.64.

Intel should still be significantly ahead, and frankly TSMC's claims seem suspect.

 

[ShintaiDK]

The fact that TSMC already rebrands 20nm as 16nm. Not to mention their previous long history of too optimistic predictions means they have to show before believing.

 

[Nothingness]

But thats before yield. Not to mention if the chips can actually perform as required or not. Its quite obvious from 20nm that the amount of theoretical chips and actually useable chips is a completely different world.

We're talking about Intel process, right? So the yields are supposed to be very high (and 20nm isn't an Intel process so can't be used as a comparison).

I agree that for other foundries that'd be different, but in that case the >500M 100mm2 chips for 90k wafers/month would be correct unless Intel has been lying when they claimed their yields are stellar and I'm convinced they don't lie

 

[ShintaiDK]

We're talking about Intel process, right? So the yields are supposed to be very high (and 20nm isn't an Intel process so can't be used as a comparison).

I agree that for other foundries that'd be different, but in that case the >500M 100mm2 chips for 90k wafers/month would be correct unless Intel has been lying when they claimed their yields are stellar and I'm convinced they don't lie

I was talking about TSMC. Intel doesnt make 20nm.

But its something often forgotten in the PR. Could Intel have released 14nm with (TSMC yields) long ago? Absolutely.

 

[Nothingness]

I was talking about TSMC. Intel doesnt make 20nm.

We were discussing Intel (you included when you talked about the 90k wafers/month) and you changed the subject without notification. How do you dare getting back on the topic thread? :biggrin:

But its something often forgotten in the PR. Could Intel have released 14nm with (TSMC yields) long ago? Absolutely.

Definitely agree.

 

[AllDayBreakfast]

How sustainable is TSMCs cap ex spending though? What I don't get is how they're spending ~$12B a year and putting 80% of that towards leading edge when leading edge is ~20% of revenue compared to Intel spending about $10B to support almost 80-100% of revenue at the leading edge. How do you maintain that?

 

[ShintaiDK]

How sustainable is TSMCs cap ex spending though? What I don't get is how they're spending ~$12B a year and putting 80% of that towards leading edge when leading edge is ~20% of revenue compared to Intel spending about $10B to support almost 80-100% of revenue at the leading edge. How do you maintain that?

The difference is Intel shift its nodes for the entire production rather fast.

If you look at TSMC, they have huge amount of production between 40 and 180nm. So for TSMC they will keep earning money on that node for the next 20 years. The problem is of course, that the revenue value quickly go down when the node isnt leading edge.

 

[witeken]

What I don't get is how they're spending ~$12B a year and putting 80% of that towards leading edge

Source for that 80%?

In any case, the leading edge is very important for a foundry's growth; else you will end up like UMC, small and forgotten. TSMC's nodes have, like you point out, a longer tail than Intel's.

 

[AllDayBreakfast]

Q4 14 Earnings call:

Lora Ho: More than 80% of the planned CapEx is budgeted for advanced technologies, while 8-inch capacity, tools for specialty technologies and back-end capacity investment constitute the rest of the 20% of 2015 budget.

 

[Khato]

TSMC's nodes have, like you point out, a longer tail than Intel's.

Is that going to be the case going forward though? Namely, what are the reasons why TSMC continues to generate so much revenue on their legacy process nodes? The basic answer is that there's a large pool of customers for whom the benefits of the smaller process nodes in no way justify the increased cost. (Namely, lower volume production is mostly stuck on older process nodes due to the high cost of design + masks for leading edge.)

I somewhat wonder if 20nm for example will pretty much disappear once 16FF comes around, and likewise with 16FF being replaced by 16FF+. Basically, there may be no reason to continue production except to support existing products and just transition the remainder of capacity to the new node.

 

[Fjodor2001]

An update on TSMC's 10 nm process tech:

http://www.kitguru.net/components/a...lidation-chips-with-quad-core-arm-cortex-a57/

TSMC builds first 10nm validation chip with quad-core Cortex-A57

Taiwan Semiconductor Manufacturing Co. has announced that it had produced the first verification chips for its 10nm manufacturing technology. The world’s largest contract maker of semiconductors plans to start risk production using 10nm fabrication process late this year and to initiate high-volume manufacturing in late 2016 or in 2017.
[...]
TSMC unveiled the first details regarding its 10nm fabrication technology earlier this year. The company’s 10nm manufacturing process will have 110 per cent higher logic density compared to its 16nm FinFET+ (CLN16FF+) process tech, 20 per cent higher clock-rate potential at the same power and 40 per cent lower power consumption at the same frequency.
[...]
It is interesting to note that TSMC still has plans to introduce a version of 10nm fabrication process that will use extreme ultraviolet (EUV) lithography production tools. Thanks to 13.5nm wavelength of EUV lasers, it will be possible to “draw” finer elements of chips without using tricky multiple-patterning techniques and implementing additional metal layers that complicate production process and make it more expensive. EUV also promises to bring significant benefits in terms of yield and cycle time. Since EUV will eliminate need for multi-patterning during production, design process of chips will get a bit simpler, which will let smaller companies to take advantage of ultra-thin FinFET process technologies.

 

[Fjodor2001]

By the way, what's Intel's position on EUV currently. Will they introduce that for 10 nm, or only later?

Apparently TSMC will design a 10 nm EUV process. Although reading the article, I get the impression that it is not certain if it'll be for the first version of their 10 nm process tech.

 

[Fjodor2001]

Also interesting to note that TSMC will initiate high-volume production of 10 nm in late 2016 or 2017. It sounds like they mean late 2016 or early 2017, but reading it strictly aren't they leaving a window open all the way until the end of 2017?

 

[ShintaiDK]

Yes, and arcording to TSMC they shipped 16FF since 2014. Not to mention 28nm since 2010.

 

[Phynaz]

Nobody's using EUV for 10nm production.

http://www.eetimes.com/document.asp?doc_id=1327056

 

[Fjodor2001]

Nobody's using EUV for 10nm production.

http://www.eetimes.com/document.asp?doc_id=1327056

How about this then:

"It is interesting to note that TSMC still has plans to introduce a version of 10nm fabrication process that will use extreme ultraviolet (EUV) lithography production tools."

 

[Phynaz]

Where does it say it will be used for production? Oh, wait, it doesn't.

I can't believe you think kit guru knows more about this than Imec. Did you even bother to read the link I provided?

 

[Fjodor2001]

Where does it say it will be used for production? Oh, wait, it doesn't.

I can't believe you think kit guru knows more about this than Imec. Did you even bother to read the link I provided?

They don't have to state that explicitly. Do you think TSMC would create a complete 10 nm EUV process tech just for fun?

Also, the Kitguru article is from a later date than the article you linked to. Things can change over time.

 

[Phynaz]

The article I linked to was a day old. Did TSMC change their EUV plans in a day?

Again, do you have any idea who Imec is? Maybe you should go read up on them so you can form an informed opinion.

 

[Fjodor2001]

The article I linked to was a day old. Did TSMC change their EUV plans in a day?

Again, do you have any idea who Imec is? Maybe you should go read up on them so you can form an informed opinion.

Maybe you should take the time to read the article you yourself linked to. Here's a quote from page 3:

It’s also possible EUV could arrive in time to be retrofitted into a sort of second-generation 10nm process. If so, it could handle one or more of the triple-patterning layers, although the machines would slow overall throughput. In addition, the systems are so expensive whether they actually lowered 10nm costs would depend on some creative accounting on their depreciation cycles.

“The decisions for 10nm have been taken to a large extent, but that doesn’t mean EUV won’t be retrofitted for it,” said Van den Hove of Imec in a press conference. “I know several companies are very eager to use EUV at the 10nm node,” he said.

 

[Systems analyst]

See:
http://optics.org/news/6/6/31
Trumpf are building a production facility for EUV lasers. They supply ASML. On stream in 2017.

ASML confirm order for 15 machines:
http://optics.org/news/6/4/31
"Before the latest update, Wennink had said that ASML was planning to ship 12 EUV systems during 2016, before ramping up to 24 systems in 2017 and 48 in 2018 as the technology becomes more widely applied."
"As well as the smaller feature sizes possible with EUV, the new systems should lead to much shorter processing cycle times – because with more conventional lithography systems the only way to create such small features would be to use multiple patterning steps, with as many as ten passes required."

It could be that Intel, being in the lead, had to use multiple patterning, in the absence of EUV machines of sufficient maturity; maybe they will update to EUV, to reduce costs.

 

[carop]

It could be that Intel, being in the lead, had to use multiple patterning, in the absence of EUV machines of sufficient maturity; maybe they will update to EUV, to reduce costs.

A node with a 1Xnm HP (Half Pitch) has different EUV mask requirements than a node with 2Xnm HP. According to Intel and Toshiba, there are significant infrastructure gabs for 1Xnm HP EUV mask.

The Intel 10nm node logic design rules will somewhat be more similar to 1Xnm memory design rules. Using the 14nm node scale factors, the Intel 10nm node design rules look as follows:

Fin Pitch: 30nm (SAQP)
Gate Pitch: 54nm
Metal0: 40nm (SADP?)
Metal1: 54nm (SADP)
Metal2: 34nm (SAQP)

There will be at least one 1Xnm HP critical metal layer that will need quadruple patterning (SAQP).

Metal0, the local interconnect, is right on the edge of double patterning (SADP). The usual 0.7x scale factor gives a pitch size of 40nm. If Intel uses a more aggressive Metal0 scale factor, it will also need SAQP.

Intel 14nm Layer Pitches:

Intel EUV Readiness:

Toshiba EUV Mask: