[DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

[raghu78]

28nm started at around 7500$ per wafer back then. And I doubt its under 2000$ today. I would expect 20nm to be around 10000$.

Wafer ASP from TSMC doesnt say much. Since they have so enormous legacy nodes for all the companies that cant afford or doesnt need any better. Hell, TSMCs main capacity is still 200mm wafers.

20nm with and without FF is still expected to be around 4000$ per wafer in 2016.

I was being conservative for 20nm.

http://www.eetimes.com/author.asp?section_id=36&doc_id=1322399

"The next logical technology node is 20 nm HKMG, and TSMC is projecting 20 nm will represent 10% of its 2014 revenues ($2.2 billion to $2.3 billion) and 20% of its fourth-quarter revenues ($1.10 billion to $1.15 billion). With the capacity of 60,000 wafers per month (WPM), the average price for 20 nm wafers in the fourth quarter at $1.1 billion will be around $6,000. This is a relatively large increase in pricing compared with 28 nm wafers, which sell at $4,500.00 to $5,000.00. If TSMC achieves its projection for 20 nm, the company will have 95% of the 20 nm foundry market in the fourth quarter 2014."

 

[ShintaiDK]

Initial 14/16nm wafers will cost around 16000$.

TSMC currently sell 20nm wafers in the 10000$ area.

28nm is cheaper than 20 and 14/16nm per transistor. Even after 2 years of high volume production.

 

[witeken]

Source?

 

[ShintaiDK]

Source?

http://forums.anandtech.com/showpost.php?p=36495911&postcount=150

 

[ShintaiDK]

There is also an extra hidden cost included at 20nm and below:

However, what really shines the light on “share and share alike” is that at 20nm, designers will also be required to purchase new double patterning software, and do additional work in the design layout and verification to enable the actual double patterning processes in the fab. Like the earlier manufacturing tools, the double pattern checking and decomposition capability requires a whole new software engine under the hood to properly analyze the layout. But unlike the earlier layout issues, double patterning violations can be much more pervasive, and fixing them is mandatory, not just recommended.

 

[ancientarcher]

There is also an extra hidden cost included at 20nm and below:

20nm and higher nodes will have a higher cost per transistor solely because of double patterning.

I am quite surprised at how the discussion has moved to 10nm. That is far far off guys! For those who think Intel will be ready with a 10nm product on the shelves in mid-2016, do you really think Intel will be able to recover the cost of its investment in 14nm in a year and half? Doesn't matter if Intel is ready to do 10nm production by 2016, it WILL NOT do it if it hasn't recovered the costs for its 14nm fabs (and at what capex - at $11bn annually, sum it up)

 

[Exophase]

http://forums.anandtech.com/showpost.php?p=36495911&postcount=150

That's funny, IBS (which should be the same source you're citing) gave VERY different numbers in this paper:

http://www.soiconsortium.org/pdf/Economic_Impact_of_the_Technology_Choices_at_28nm_20nm.pdf

Initial wafer cost of 20nm planar HKMG at $4000 and $5338 for 20nm with FinFETs (ie, TSMC's 16nm process). Where did you get your chart from?

 

[Homeles]

That's funny, IBS (which should be the same source you're citing) gave VERY different numbers in this paper:

http://www.soiconsortium.org/pdf/Economic_Impact_of_the_Technology_Choices_at_28nm_20nm.pdf

Initial wafer cost of 20nm planar HKMG at $4000 and $5338 for 20nm with FinFETs (ie, TSMC's 16nm process). Where did you get your chart from?

The earliest usage of this graph I could find is from here:
http://semiengineering.com/double-patterning-sharing-benefit-burden/

But it's since been posted everywhere.

 

[Exophase]

The earliest usage of this graph I could find is from here:
http://semiengineering.com/double-patterning-sharing-benefit-burden/

But it's since been posted everywhere.

Okay, well since that post is even older than the paper I linked and doesn't really cite its sources I think it's fair to say it shouldn't be taken very seriously.

Then again, the paper I linked is a massive FD-SOI promotional piece with some truly amazing claims, so I think it should be taken with some salt too (ie, if FD-SOI is so amazing why is it that almost no one has even been talking about using it)

 

[ShintaiDK]

Okay, well since that post is even older than the paper I linked and doesn't really cite its sources I think it's fair to say it shouldn't be taken very seriously.

Then again, the paper I linked is a massive FD-SOI promotional piece with some truly amazing claims, so I think it should be taken with some salt too (ie, if FD-SOI is so amazing why is it that almost no one has even been talking about using it)

The numbers you linked I got as well in my second image. But there is the small writing to take into account. Those prices are estimated for 2 years in full volume production. The initial wafer cost is something entirely different. Also why Qualcomm for example first will have 20nm MPUs in Q1/2015.

 

[NostaSeronx]

Then again, the paper I linked is a massive FD-SOI promotional piece with some truly amazing claims, so I think it should be taken with some salt too (ie, if FD-SOI is so amazing why is it that almost no one has even been talking about using it)

STMicroelectronics will be using it for there IoT lineup.

http://www.st.com/web/en/press/en/t3502
----

UTBB SOI can be more dense than FinFETs if a fabless plans to go LP or HPL.

SLVT = Highest Leakage, Lowest Delay
SHVT = Lowest Leakage, Highest Delay

FDSOI w/ FBB+RBB => Gate Pitch is maintained.

The decision to go FinFETs to me is an excuse to blame the foundry. Since, most of the problems will arise with the Foundry. Where FDSOI most of the issues come from the low supply of SOI wafers. Which is currently being remedied by SOITEC, ShinEtsu, etc.

 

[Exophase]

The numbers you linked I got as well in my second image. But there is the small writing to take into account. Those prices are estimated for 2 years in full volume production. The initial wafer cost is something entirely different. Also why Qualcomm for example first will have 20nm MPUs in Q1/2015.

No, the prices are quoted for initial offering. Go read the document again. The prices for two years later are given too, but they're not that much lower.

20nm availability isn't the only driver for the Cortex-A57 Qualcomm parts - there were never very high hopes for any A57 part coming out in 2014. On the other hand, they have 20nm LTE modems in products now. I suppose those are supposed to be high cost, low volume parts?

 

[Exophase]

STMicroelectronics will be using it for there IoT lineup.

http://www.st.com/web/en/press/en/t3502

Well there you have it, the only company committing to using FDSOI for products is the one who developed the process.

 

[NostaSeronx]

Well there you have it, the only company committing to using FDSOI for products is the one who developed the process.

Jean-Marc Chery, executive vice president and general manager of embedded processing solutions at ST, told Electronics 360 that the number of FDSOI IC designs in development has risen to 15.

These are the 28-nm versions;

Of the 15 design wins six are in the communications infrastructure category and 9 are for consumer applications and ST's STB design is only counted as one of these. "There is one application that makes use of very low voltage, 0.6V operation," Chery said, indicating that designers of power-constrained chips for Internet of Things (IoT) applications are also looking at FDSOI.

Any designs on 20-nm or now called 14-nm FDSOI at GlobalFoundries is unknown.

Chery said: "By Q4 we will be ready for mass production in Q1. We will have an open, dual-foundry source for FDSOI." When asked if that second source would be Globalfoundries, Chery added: "We have an agreement with Globalfoundries that is not exclusive."

Chery said ST would be able to meet customer ramp up of FDSOI products from its Crolles 300-mm wafer fab near Grenoble, France and that Globalfoundries would be in position to help with volume production at its Dresden fab in 2014. Chery showed the audience that the next node – 14-nm UTBB FDSOI – will start prototyping in 2014 or 2015 to be followed by 10-nm UTBB FDSOI in 2016 or 2017.

All the articles are 2013 and 2014 from which I grabbed them.

Samsung's FinFETs = Fab 8
STMicroelectronic's FDSOI = Fab 1 and Fab 7(RFSOI)

 

[Exophase]

Back to what I first said: if FD-SOI is so amazing why is it that almost no one has even been talking about using it? Not counting people in forums speculating about who will be using it.

 

[teejee]

and the payment of the foundry tax

You are ruining your argument by talking about your imaginary "foundry tax" all the time.

Splitting a company into one manufacturing part and one product part does not affect margin measured in percent (assuming large companies, otherwise a few benefits by being larger, like more efficient administration ). This is basic finance.

 

[witeken]

You are ruining your argument by talking about your imaginary "foundry tax" all the time.

Splitting a company into one manufacturing part and one product part does not affect margin measured in percent (assuming large companies, otherwise a few benefits by being larger, like more efficient administration ). This is basic finance.

http://forums.anandtech.com/showpost.php?p=36487925&postcount=82

Apparently not.

 

[AtenRa]

Back to what I first said: if FD-SOI is so amazing why is it that almost no one has even been talking about using it? Not counting people in forums speculating about who will be using it.

I believe it is because of two reasons,

First the FD-SOI process is late than the Planar, that has a significant impact for the high-end players. 20nm FD-SOI may not be ready until even late 2015. 28nm FD-SOI was only made ready in 2013.

Secondly, at high volumes FD-SOI looses most of its price advantage it has over Bulk.

Combine those two and the big players are not interested for FD-SOI.

 

[teejee]

http://forums.anandtech.com/showpost.php?p=36487925&postcount=82

Apparently not.

First, of course Intel can have lower cost than a specific competitor by being more efficient, that has nothing to do with them being a foundry or not.

second, I'm not convinced that Intel has lower cost than TSMC just because of this table. It depends a lot on how you handle the huge investments in your budget and other accounting strategies.

 

[Exophase]

I believe it is because of two reasons,

First the FD-SOI process is late than the Planar, that has a significant impact for the high-end players. 20nm FD-SOI may not be ready until even late 2015. 28nm FD-SOI was only made ready in 2013.

Secondly, at high volumes FD-SOI looses most of its price advantage it has over Bulk.

Combine those two and the big players are not interested for FD-SOI.

Right, which paints a pretty different picture from the PDF I linked, which talks about FDSOI costing half as much as FinFETs for large dies.

 

[NostaSeronx]

Back to what I first said: if FD-SOI is so amazing why is it that almost no one has even been talking about using it? Not counting people in forums speculating about who will be using it.

28-nm FDSOI is largely aimed at the low power/low leakage crowd. (These guys are on the 90/65/40-nm nodes still.)

Routers, Cable-top boxes, Phones, Automobiles, Embedded, Wearable, and etc.

14-nm FDSOI is where the bomb is dropped. 65-nm TSVs - Free Reverse/Forward Body Biasing - Straining for High Performance - etc

14-nm FDSOI has hit prototyping in Q2 2014. With sampling of chips expected to occur around Q4 2014. Then, maybe device volume production sometime late 2015 or early 2016. With GlobalFoundries dropping investment in the XM node, 14-nm FDSOI is expected to appear before the 14-nm LPE/LPP node options.

From what I can get 14-nm FDSOI is about ~30% overall cheaper than 14-nm FinFETs*. This is ignoring designer intelligence with FBB and RBB though. Add that if a designer is real smart they can make a design with ABB, adaptive body biasing. (Samsung, Qualcomm, STMicroelectronics have patents for it.)

*No indication of which node, FF/XM/LPE or LPP/FF+.

 

[videogames101]

Sorry, but no one is even taping out 20nm designs, much less 16. Forget about 10.

 

[Arachnotronic]

First, of course Intel can have lower cost than a specific competitor by being more efficient, that has nothing to do with them being a foundry or not.

second, I'm not convinced that Intel has lower cost than TSMC just because of this table. It depends a lot on how you handle the huge investments in your budget and other accounting strategies.

Even if Intel has higher per-wafer costs, I'd imagine that Intel's yields are simply much better when they go into "production" which may give them better overall cost.

However, this is speculative and should not be used for more than it is: the opinion of somebody on the internet

 

[NostaSeronx]

Sorry, but no one is even taping out 20nm designs, much less 16. Forget about 10.

Our 16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today.
Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs
are compatible.

We will receive our first customer product tapeout this month. About 15 products planned for 2014, another about 45 in 2015. Volume production
is planned in 2015. Since 95% tools of 16 and 20 are common, we will ramp them in the same gigafabs in TSMC. 16 FinFET yield learning curve is
very steep today and has already caught up with 20 SoC. This is a unique advantage in TSMC 16-nanometer

From TSMC themselves. This is talking about 16-nm FF and 16-nm FF+.

GlobalFoundries has stated they have 20-nm LPM and 14-nm LPE tapeouts but didn't specify the number.

Samsung, GlobalFoundries, and TSMC expect some customers to be on 20-nm for a long time. While others are eager for FinFETs even though cost per transistor increases rather than decreases.

 

[Exophase]

Sorry, but no one is even taping out 20nm designs, much less 16. Forget about 10.

What are you saying exactly? There are literally 20nm chips in products right now..

And to all of you saying no 20nm SoCs in 2014, I guess you expect iPhone 6 to be using a 28nm SoC. We'll see.