Arachnotronic
Lifer
- Mar 10, 2006
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I can accept their 10nm timeline, it is reasonable. But I find it difficult to accept their claims of matching or near-matching Intel's parametric FOM and design rules.
I agree. At 16FF/16FF+ they're at 90nm gate pitch, matching Intel's 22nm. 64nm minimum metal, which is ahead of the 80nm minimum metal Intel had at 22nm, but both well behind the 70nm/52nm of Intel's 14nm.
That said, TSMC claims a 2.2x gate density improvement in going from 16FF+ -> 10nm, so if we look at the metric GP*MxP, then TSMC will go from (90)(64) = 5760 -> (X)(Y) ~= 2618
Assuming they scale metal + gate pitch roughly equally, then the pitches should be:
GP = 60nm
MxP = 44nm
If we take Intel's 14nm and scale by a factor of 2 (Intel claims >2x density improvement over 14nm at 10nm, but I want to look at the "best case" for TSMC), then we go from 70nm GP -> 49nm, and then in metal we go from 52nm -> 36nm.
Realistically, though, Intel already made a big jump (>2x) in metals at 14nm and was behind 2x scaling with gate pitch, so I think Intel will reverse that (go >2x with gate, and ~2x with metal).
At any rate, assuming 2x scaling for both min metal and gate pitch gives us the 49nm GP and 36nm minimum metal, which should mean the GP * MxP metric for Intel 10nm winds up at (49)(36) = 1764
1764/2618 = 0.64.
Intel should still be significantly ahead, and frankly TSMC's claims seem suspect.